Array ( [0] => {{Short description|Open-source CPU hardware instruction set architecture}} [1] => {{Use dmy dates|date=June 2016}} [2] => {{Infobox CPU architecture [3] => | name = RISC-V [4] => | image = RISC-V-logo.svg [5] => | designer = [[University of California, Berkeley]] [6] => | bits = [[32-bit computing|32]], [[64-bit computing|64]], [[128-bit computing|128]] [7] => | introduced = {{Start date and age|2014|08|06|p=1}}{{Cite conference |last1=Asanović |first1=Krste |author1-link=Krste Asanović |last2=Patterson |first2=David A. |author2-link=David A. Patterson (computer scientist) |date=August 6, 2014 |title=Instruction Sets Should Be Free: The Case For RISC-V |url=http://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.pdf |id=UCB/EECS-2014-146 |publisher=EECS Department, University of California, Berkeley}} [8] => | version = {{plainlist| [9] => * unprivileged ISA 20191213, [10] => * privileged ISA 20211203 [11] => }} [12] => | design = [[Reduced instruction set computer|RISC]] [13] => | type = [[Load–store architecture|Load–store]] [14] => | encoding = Variable [15] => | branching = Compare-and-branch [16] => | endianness = Little{{rp|page=9}}{{efn|Big and bi-endianness supported through non-standard variants; instructions are always little-endian.{{rp|pages=vi, 9–10}}}} [17] => | page size = 4 KiB [18] => | extensions = {{plainlist| [19] => * '''M''': Multiplication [20] => * '''A''': Atomics – LR/SC & fetch-and-op [21] => * '''F''': Floating point (32-bit) [22] => * '''D''': {{abbr|FP|Floating point}} Double (64-bit) [23] => * '''Q''': {{abbr|FP|Floating point}} Quad (128-bit) [24] => * '''Zicsr''': Control and status register support [25] => * '''Zifencei''': [[Memory barrier|Load/store fence]] [26] => * '''C''': Compressed instructions (16-bit) [27] => * '''J''': Interpreted or JIT-compiled languages support [28] => }} [29] => | open = Yes, royalty free [30] => | gpr = {{plainlist| [31] => * 16 [32] => * 32 [33] => }} (Includes one [[always-zero register]]) [34] => | fpr = {{plainlist| [35] => * 32 [36] => }} (Optional. Width depends on available extensions) [37] => }} [38] => [39] => '''RISC-V'''{{Efn|The designation V (Roman numeral '5') represents RISC-V as the 5th generation [[reduced instruction set computer]] (RISC) [[Computer architecture|architecture]] that was developed at the [[University of California, Berkeley]] since 1981.{{cite web |first=Roddy |last=Urquhart |title=What Does RISC-V Stand For? A brief history of the open ISA |date=29 March 2021 |work=Systems & Design: Opinion |publisher=Semiconductor Engineering |url=https://semiengineering.com/what-does-risc-v-stand-for/}}}} (pronounced "risk-five"{{rp|page=1}}) is an [[open standard]] [[instruction set architecture]] (ISA) based on established [[reduced instruction set computer]] (RISC) principles. Unlike most other ISA designs, RISC-V is provided under [[royalty-free]] [[open-source license]]s. Many companies are offering or have announced RISC-V hardware; open source operating systems with RISC-V support are available, and the instruction set is supported in several popular software [[toolchain]]s. [40] => [41] => The project began in 2010 at the University of California, Berkeley. There are now members in over 70 countries contributing and collaborating to define RISC-V open specifications. RISC-V International, the non-profit managing RISC-V, is currently headquartered in [[Switzerland]].{{cite web |title=About RISC-V, RISC-V International is the global non-profit home of the open standard RISC-V Instruction Set Architecture (ISA) |publisher=RISC-V International |url=https://riscv.org/about/}}{{cite web |title=RISC-V To Move HQ to Switzerland Amid Trade War Concerns |date=28 November 2019 |publisher=EE Times Europe |url=https://www.eetimes.eu/risc-v-to-move-hq-to-switzerland-amid-trade-war-concerns/}} [42] => [43] => ==Overview== [44] => As a RISC architecture, the RISC-V ISA is a [[load–store architecture]]. Its floating-point instructions use [[IEEE 754]] floating-point. Notable features of the RISC-V ISA include: instruction bit field locations chosen to simplify the use of [[Multiplexer#Digital multiplexers|multiplexers]] in a CPU,{{rp|page=17}} a design that is architecturally neutral,{{Dubious||reason=the design of an architecture necessarily favors itself and thus is not 'architecturally neutral'; no support elsewhere in article|date=November 2023}} and a fixed location for the sign bit of [[immediate value]]s to speed up [[sign extension]].{{rp|page=17}} [45] => [46] => The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of [[32-bit computing|32-bit]] naturally aligned instructions, and the ISA supports variable length extensions where each instruction can be any number of [[16-bit computing|16-bit]] parcels in length.{{rp|pages=7{{hyp}}10}} Extensions support small [[embedded system]]s, [[personal computer]]s, [[supercomputer]]s with vector processors, and warehouse-scale [[parallel computing|parallel computers]]. [47] => [48] => The instruction set specification defines 32-bit and [[64-bit computing|64-bit]] [[address space]] variants. The specification includes a description of a [[128-bit computing|128-bit]] flat address space variant, as an extrapolation of 32- and 64-bit variants, but the 128-bit ISA remains "not frozen" intentionally, because {{as of|2023|lc=y}}, there is still little practical experience with such large memory systems.{{rp|page=41}} [49] => [50] => Unlike other academic designs which are typically optimized only for simplicity of exposition, the designers intended that the RISC-V instruction set be usable for practical computers. As of June 2019, version 2.2 of the user-space ISA and version 1.11 of the privileged ISA are [[Freeze (software engineering)|frozen]], permitting software and hardware development to proceed. The user-space ISA, now renamed the Unprivileged ISA, was updated, ratified and frozen as version 20191213. An external debug specification is available as a draft, version 0.13.2. [51] => [52] => ==Rationale== [53] => [[File:Yunsup Lee holding RISC V prototype chip.jpg|thumb|RISC-V processor prototype, January 2013]] [54] => [55] => [[CPU design]] requires design expertise in several specialties: electronic [[Logic gate|digital logic]], [[compiler]]s, and [[operating system]]s. To cover the costs of such a team, commercial vendors of processor intellectual property (IP), such as [[Arm Ltd.]] and [[MIPS Technologies]], charge [[Royalty payment|royalties]] for the use of their designs, [[patent]]s and [[copyright]]s.{{cite web |url=https://semiaccurate.com/2013/08/07/a-long-look-at-how-arm-licenses-chips/ |title=A long look at how ARM licenses chips: Part 1 |last=Demerjian |first=Chuck |date=August 7, 2013 |publisher=SemiAccurate}}{{cite web |url=https://semiaccurate.com/2013/08/08/how-arm-licenses-its-ip-for-production/ |title=How ARM licenses its IP for production: Part 2 |last=Demerjian |first=Chuck |date=August 8, 2013 |publisher=SemiAccurate}}{{cite web|url=https://www.hackster.io/news/wave-computing-closes-its-mips-open-initiative-with-immediate-effect-zero-warning-e88b0df9acd0|title=Wave Computing Closes Its MIPS Open Initiative with Immediate Effect, Zero Warning|date=2019-11-15}} They also often require [[non-disclosure agreement]]s before releasing documents that describe their designs' detailed advantages. In many cases, they never describe the reasons for their design choices. [56] => [57] => RISC-V was begun with a goal to make a practical ISA that was open-sourced, usable academically, and deployable in any hardware or software design without royalties.{{rp|page=1}} Also, justifying rationales for each design decision of the project are explained, at least in broad terms. The RISC-V authors are academics who have substantial experience in computer design, and the RISC-V ISA is a direct development from a series of academic computer-design projects, especially [[Berkeley RISC]]. RISC-V was originated in part to aid all such projects.{{rp|page=1}} [58] => [59] => To build a large, continuing community of users and thereby accumulate designs and software, the RISC-V ISA designers intentionally support a wide variety of practical use cases: compact, performance, and low-power real-world implementations{{rp|pages=1{{hyp}}2,153{{hyp}}154}} without over-architecting for a given [[microarchitecture]].{{rp|page=1}}{{cite web |last1=Celio |first1=Christopher |last2=Love |first2=Eric |title=riscv-sodor: educational microarchitectures for risc-v isa |url=https://github.com/ucb-bar/riscv-sodor |website=GitHub |publisher=Regents of the University of California |access-date=2019-10-25}}{{cite web |last=Celio |first=Christopher |title=CS 152 Laboratory Exercise 3 |url=http://www-inst.eecs.berkeley.edu/~cs152/sp14/handouts/lab3.pdf |website=UC Berkeley |publisher=Regents of the University of California |access-date=12 February 2015 |archive-url=https://web.archive.org/web/20150212211808/http://www-inst.eecs.berkeley.edu/~cs152/sp14/handouts/lab3.pdf |archive-date=12 February 2015 |url-status=dead}} The requirements of a large base of contributors is part of the reason why RISC-V was engineered to address many possible uses. [60] => [61] => The designers' primary assertion is that the instruction set is the key interface in a computer as it is situated at the interface between the hardware and the software. If a good instruction set were open and available for use by all, then it can dramatically reduce the cost of software by enabling far more reuse. It should also trigger increased competition among hardware providers, who can then devote more resources toward design and less for software support. [62] => [63] => The designers maintain that new principles are becoming rare in instruction set design, as the most successful designs of the last forty years have grown increasingly similar. Of those that failed, most did so because their sponsoring companies were financially unsuccessful, not because the instruction sets were technically poor. Thus, a well-designed open instruction set designed using well-established principles should attract long-term support by many vendors. [64] => [65] => RISC-V also encourages academic usage. The simplicity of the integer subset permits basic student exercises, and is a simple enough ISA to enable software to control research machines. The variable-length ISA provides room for instruction set extensions for both student exercises and research,{{rp|page=7}} and the separated privileged instruction set permits research in operating system support without redesigning compilers. RISC-V's open intellectual property paradigm allows derivative designs to be published, reused, and modified. [66] => [67] => ==History== [68] => The term ''[[Reduced instruction set computer|RISC]]'' dates from about 1980. Before then, there was some knowledge (see [[John Cocke (computer scientist)|John Cocke]]) that simpler computers can be effective, but the design principles were not widely described. Simple, effective computers have always been of academic interest, and resulted in the RISC instruction set [[DLX]] for the first edition of ''Computer Architecture: A Quantitative Approach'' in 1990 of which [[David Patterson (computer scientist)|David Patterson]] was a co-author, and he later participated in the RISC-V origination. DLX was intended for educational use; academics and hobbyists implemented it using [[field-programmable gate array]]s (FPGA), but it was never truly intended for commercial deployment. [[ARM architecture|ARM]] CPUs, versions 2 and earlier, had a public-domain instruction set and are still supported by the [[GNU Compiler Collection]] (GCC), a popular [[free software|free-software]] compiler. Three open-source [[semiconductor intellectual property core|cores]] exist for this ISA, but were never manufactured. [[OpenRISC]] is an open-source ISA based on DLX, with associated RISC designs, and is fully supported with GCC and [[Linux]] implementations, although it too has few commercial implementations. [69] => [70] => [[Krste Asanović]] at the [[University of California, Berkeley]], had a research requirement for an open-source computer system, and in 2010, he decided to develop and publish one in a "short, three-month project over the summer" with several of his graduate students. The plan was to aid both academic and industrial users.{{cite web |url=https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.pdf |title=Instruction Sets Should be Free |last=Asanović |first=Krste |author-link=Krste Asanović |website=U.C. Berkeley Technical Reports |publisher=Regents of the University of California |access-date=15 November 2016}} David Patterson at Berkeley joined the collaboration as he was the originator of the Berkeley RISC, and the RISC-V is the eponymous fifth generation of his long series of cooperative RISC-based research projects at the University of California, Berkeley ([[Berkeley RISC#RISC I|RISC-I]] and [[Berkeley RISC#RISC II|RISC-II]] published in 1981 by Patterson, who refers{{cite tech report |last=Chen |first=Tony |author2=[[David Patterson (computer scientist)|David A. Patterson]] |date=2016-01-24 |title=RISC-V Geneology |institution=University of California at Berkeley |number=UCB/EECS-2016-6 |url=http://www.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-6.html }} to the SOAR architecture{{cite tech report |last=Samples |first=Alan Dain |last2=Klein |first2=Mike |last3=Foley |first3=Pete |date=1985 |title=SOAR Architecture |institution=University of California, Berkeley |number=UCB/CSD-85-226 |url=http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/5940.html }} from 1984 as "RISC-III" and the SPUR architecture{{cite tech report |last=Hill |first=Mark Donald |collaboration=Susan J. Eggers, James Richard Larus, George S. Taylor, Glenn D. Adams, Bidyut Kumar Bose, Garth A. Gibson, Paul Mark Hansen, John Keller, Shing I. Kong, Corinna Grace Lee, Daebum Lee, J. M. Pendleton, Scott Allen Ritchie, David A. Wood, Benjamin G. Zorn, Paul N. Hilfinger, D. A. Hodges, Randy H. Katz, John K. Ousterhout, and [[David Patterson (computer scientist)|David A. Patterson]] |date=December 1985 |title=SPUR: A VLSI Multiprocessor Workstation |institution=University of California, Berkeley |number=UCB/CSD-86-273 |url=http://www.eecs.berkeley.edu/Pubs/TechRpts/1985/6083.html}} from 1988 as "RISC-IV"). At this stage, students provided initial software, simulations, and CPU designs. [71] => [[File:Raven1ST28 June12BWRC.jpg|thumb|First Raven1 bring up ST28nm at [[Berkeley Wireless Research Center]] (BWRC) June 2012]] [72] => [73] => The RISC-V authors and their institution originally sourced the ISA documents{{cite web |url=https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-62.pdf |title=The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA |last=Asanović |first=Krste |author-link=Krste Asanović |website=U.C. Berkeley Technical Reports |publisher=Regents of the University of California |access-date=13 May 2011}} and several CPU designs under [[BSD licenses]], which allow derivative works—such as RISC-V chip designs—to be either open and free, or closed and proprietary. The ISA specification itself (i.e., the encoding of the instruction set) was published in 2011 as open source,{{cite news |last=Hruska |first=Joel |date=21 August 2014 |url=https://www.extremetech.com/computing/188405-risc-rides-again-new-risc-v-architecture-hopes-to-battle-arm-and-x86-by-being-totally-open-source |title=RISC rides again: New RISC-V architecture hopes to battle ARM and x86 by being totally open source |website=[[ExtremeTech]]}} with all rights reserved. The actual technical report (an expression of the specification) was later placed under a [[Creative Commons license]] to permit enhancement by external contributors through the RISC-V Foundation, and later RISC-V International. [74] => [75] => A full history of RISC-V has been published on the RISC-V International website. [76] => [77] => ===RISC-V Foundation and RISC-V International=== [78] => Commercial users require an ISA to be stable before they can use it in a product that may last many years. To address this issue, the RISC-V Foundation was formed in 2015 to own, maintain, and publish intellectual property related to RISC-V's definition.{{Cite news |url=https://www.economist.com/science-and-technology/2019/10/03/a-new-blueprint-for-microprocessors-challenges-the-industrys-giants |title=A new blueprint for microprocessors challenges the industry's giants |date=2019-10-03 |newspaper=The Economist |access-date=2019-11-10 |issn=0013-0613}} The original authors and owners have surrendered their rights to the foundation.{{citation needed|date=August 2023}} The foundation is led by CEO [[Calista Redmond]], who took on the role in 2019 after leading open infrastructure projects at [[IBM]].{{Cite web|title=Design Automation Conference|url=https://dac.com/|access-date=2021-02-06|website=dac.com}}{{failed verification|date=January 2023}} [79] => [80] => The founding members of RISC-V were: Andes, Antmicro, Bluespec, CEVA, Codasip, Cortus, Esperanto, Espressif, ETH Zurich, Google, IBM, ICT, IIT Madras, Lattice, lowRISC, Microchip, MIT (Csail), Qualcomm, Rambus, Rumble, SiFive, Syntacore and Technolution.{{Cite web |title=Members |url=https://riscv.org/members/ |access-date=2023-08-01 |website=RISC-V International |language=en-US}} [81] => [82] => In November 2019, the RISC-V Foundation announced that it would relocate to Switzerland, citing concerns over U.S. trade regulations.{{Cite news |date=2019-11-26 |title=U.S.-based chip-tech group moving to Switzerland over trade curb fears |language=en |work=[[Reuters]] |url=https://www.reuters.com/article/us-usa-china-semiconductors-insight-idUSKBN1XZ16L |access-date=2019-11-26}}{{Cite web |last=Cheung |first=Sunny |date=December 15, 2023 |title=Examining China’s Grand Strategy For RISC-V |url=https://jamestown.org/program/examining-chinas-grand-strategy-for-risc-v/ |access-date=2023-12-18 |website=China Brief |publisher=[[Jamestown Foundation]] |language=en-US}} As of March 2020, the organization was named RISC-V International, a Swiss nonprofit business association.{{cite web |url=https://riscv.org/risc-v-history/#international |title=RISC-V History - RISC-V International |website=RISC-V International |access-date=2020-05-14}} [83] => [84] => {{As of|2019}}, RISC-V International freely publishes the documents defining RISC-V and permits unrestricted use of the ISA for design of software and hardware. However, only members of RISC-V International can vote to approve changes, and only member organizations use the [[trademark]]ed compatibility logo.{{cite web |title=RISC-V Foundation |url=https://riscv.org/risc-v-foundation/ |publisher=RISC-V Foundation |access-date=15 March 2019 |archive-url=https://web.archive.org/web/20190410201639/https://riscv.org/risc-v-foundation/ |archive-date=10 April 2019 |url-status=dead}}{{failed verification|date=August 2023}} [85] => [86] => ===Awards=== [87] => * 2017: The Linley Group's Analyst's Choice Award for Best Technology (for the instruction set){{cite press release [88] => | title = The Linley Group Announces Winners of Annual Analysts' Choice Awards [89] => | url = http://linleygroup.com/press_detail.php?The-Linley-Group-Announces-Winners-of-Annual-Analysts-Choice-Awards-85 [90] => | publisher = The Linley Group [91] => | date = 12 January 2017 [92] => | access-date = 21 January 2018}} [93] => [94] => ==Design== [95] => [96] => ===ISA base and extensions=== [97] => RISC-V has a modular design, consisting of alternative base parts, with added optional extensions. The ISA base and its extensions are developed in a collective effort between industry, the research community and educational institutions. The base specifies instructions (and their encoding), control flow, registers (and their sizes), memory and addressing, logic (i.e., integer) manipulation, and ancillaries. The base alone can implement a simplified general-purpose computer, with full software support, including a general-purpose compiler. [98] => [99] => The standard extensions are specified to work with all of the standard bases, and with each other without conflict. [100] => [101] => Many RISC-V computers might implement the compressed instructions extension to reduce power consumption, code size, and memory use.{{rp|pages=97{{hyp}}99}} There are also future plans to support [[hypervisor]]s and [[virtualization]]. [102] => [103] => Together with the supervisor extension, S, an RVGC instruction set, which includes one of the RV base instruction sets, the G collection of extensions (which includes "I", meaning that the base is non-embedded), and the C extension, defines all instructions needed to conveniently support a general purpose [[operating system]].{{rp|pages=129, 154}} [104] => [105] => {| class="wikitable plainrowheaders" [106] => |- [107] => |+ ISA base and extensions [108] => |- [109] => ! scope="col" | Name [110] => ! scope="col" | Description [111] => ! scope="col" | Version [112] => ! scope="col" | Status{{efn-ua|name=frozen|Frozen parts are expected to have their final feature set and to receive only clarifications before being ratified.}} [113] => !Instruction count [114] => |- [115] => ! colspan=5 | Base [116] => |- [117] => ! scope="row" | {{mono|RVWMO}} [118] => | Weak Memory Ordering || 2.0 || {{Yes|Ratified}} [119] => | [120] => |- [121] => ! scope="row" | {{mono|RV32I}} [122] => | Base Integer Instruction Set, 32-bit || 2.1 || {{Yes|Ratified}} [123] => |40 [124] => |- [125] => ! scope="row" | {{mono|RV32E}} [126] => | Base Integer Instruction Set (embedded), 32-bit, 16 registers || 2.0 || {{Yes|Ratified}} [127] => |40 [128] => |- [129] => ! scope="row" | {{mono|RV64I}} [130] => | Base Integer Instruction Set, 64-bit || 2.1 || {{Yes|Ratified}} [131] => |15 [132] => |- [133] => ! scope="row" | {{mono|RV64E}} [134] => | Base Integer Instruction Set (embedded), 64-bit || 2.0 || {{Yes|Ratified}} [135] => | [136] => |- [137] => ! scope="row" | {{mono|RV128I}} [138] => | Base Integer Instruction Set, 128-bit || 1.7 || {{No|Open}} [139] => |15 [140] => |- [141] => ! colspan=5 | Extension [142] => |- [143] => ! scope="row" | M [144] => | Standard Extension for Integer Multiplication and Division || 2.0 || {{Yes|Ratified}} [145] => |{{figure space}}8 ({{mono|RV32}})
13 ({{mono|RV64}}) [146] => |- [147] => ! scope="row" | A [148] => | Standard Extension for Atomic Instructions || 2.1 || {{Yes|Ratified}} [149] => |11 ({{mono|RV32}})
22 ({{mono|RV64}}) [150] => |- [151] => ! scope="row" | F [152] => | Standard Extension for Single-Precision Floating-Point || 2.2 || {{Yes|Ratified}} [153] => |26 ({{mono|RV32}})
30 ({{mono|RV64}}) [154] => |- [155] => ! scope="row" | D [156] => | Standard Extension for Double-Precision Floating-Point || 2.2 || {{Yes|Ratified}} [157] => |26 ({{mono|RV32}})
32 ({{mono|RV64}}) [158] => |- [159] => ! scope="row" | Zicsr [160] => | Control and Status Register (CSR) Instructions || 2.0 || {{Yes|Ratified}} [161] => |6 [162] => |- [163] => ! scope="row" | Zifencei [164] => | Instruction-Fetch Fence || 2.0 || {{Yes|Ratified}} [165] => |1 [166] => |- [167] => ! scope="row" | G [168] => | Shorthand for the IMAFD_Zicsr_Zifencei base and extensions{{rp|page=129}} || {{n/a}} || {{n/a}} [169] => | [170] => |- [171] => ! scope="row" | Q [172] => | Standard Extension for Quad-Precision Floating-Point || 2.2 || {{Yes|Ratified}} [173] => |28 ({{mono|RV32}})
32 ({{mono|RV64}}) [174] => |- [175] => ! scope="row" | L [176] => | Standard Extension for Decimal Floating-Point || 0.0 || {{No|Open}} [177] => | [178] => |- [179] => ! scope="row" | C [180] => | Standard Extension for Compressed Instructions || 2.0 || {{Yes|Ratified}} [181] => |40 [182] => |- [183] => ! scope="row" | B [184] => | Standard Extension for Bit Manipulation || 1.0 || {{Yes|Ratified}} [185] => |43 [186] => |- [187] => ! scope="row" | J [188] => | Standard Extension for Dynamically Translated Languages || 0.0 || {{No|Open}} [189] => | [190] => |- [191] => ! scope="row" | T [192] => | Standard Extension for Transactional Memory || 0.0 || {{No|Open}} [193] => | [194] => |- [195] => ! scope="row" | P [196] => | Standard Extension for Packed-SIMD Instructions || 0.9.10 || {{No|Open}} [197] => | [198] => |- [199] => ! scope="row" | V [200] => | Standard Extension for Vector Operations || 1.0 || {{Yes|Ratified}} [201] => |187{{cite web |title=Vector Extension |date=November 2021 |publisher=RISC-V International |url=https://github.com/riscv/riscv-v-spec/releases/tag/v1.0}} [202] => |- [203] => ! scope="row" | Zk [204] => | Standard Extension for Scalar Cryptography || 1.0.1 || {{Yes|Ratified}} [205] => | 49 [206] => |- [207] => ! scope="row" | H [208] => | Standard Extension for Hypervisor || 1.0 || {{Yes|Ratified}} [209] => |15 [210] => |- [211] => ! scope="row" | S [212] => |Standard Extension for Supervisor-level Instructions ||1.12|| {{Yes|Ratified}} [213] => |4 [214] => |- [215] => ! scope="row" | Zam [216] => | Misaligned Atomics || 0.1 || {{No|Open}} [217] => | [218] => |- [219] => ! scope="row" | Zihintpause [220] => | Pause Hint || 2.0 || {{Yes|Ratified}} [221] => | [222] => |- [223] => ! scope="row" | Zihintntl [224] => | Non-Temporal Locality Hints || 0.3 || {{Yes|Ratified}} [225] => | [226] => |- [227] => ! scope="row" | Zfa [228] => | Additional Floating-Point Instructions || 1.0 || {{Yes|Ratified}} [229] => | [230] => |- [231] => ! scope="row" | Zfh [232] => | Half-Precision Floating-Point || 1.0 || {{Yes|Ratified}} [233] => | [234] => |- [235] => ! scope="row" | Zfhmin [236] => | Minimal Half-Precision Floating-Point || 1.0 || {{Yes|Ratified}} [237] => | [238] => |- [239] => ! scope="row" | Zfinx [240] => | Single-Precision Floating-Point in Integer Register || 1.0 || {{Yes|Ratified}} [241] => | [242] => |- [243] => ! scope="row" | Zdinx [244] => | Double-Precision Floating-Point in Integer Register || 1.0 || {{Yes|Ratified}} [245] => | [246] => |- [247] => ! scope="row" | Zhinx [248] => | Half-Precision Floating-Point in Integer Register || 1.0 || {{Yes|Ratified}} [249] => | [250] => |- [251] => ! scope="row" | Zhinxmin [252] => | Minimal Half-Precision Floating-Point in Integer Register || 1.0 || {{Yes|Ratified}} [253] => | [254] => |- [255] => ! scope="row" | Zmmul [256] => | Multiplication Subset of the M Extension || 1.0 || {{Yes|Ratified}} [257] => | [258] => |- [259] => ! scope="row" | Ztso [260] => | Total Store Ordering || 1.0 || {{Yes|Ratified}} [261] => | [262] => |} [263] => [264] => {{Notelist-ua}} [265] => [266] =>
[267] => {| class="wikitable" style="text-align:center;" [268] => |+ 32-bit RISC-V instruction formats [269] => |- [270] => ! rowspan=2 | Format [271] => ! colspan=32 | Bit [272] => |- [273] => ! 31 !! 30 !! 29 !! 28 !! 27 !! 26 !! 25 !! 24 !! 23 !! 22 !! 21 !! 20 !! 19 !! 18 !! 17 !! 16 !! 15 !! 14 !! 13 !! 12 !! 11 !! 10 !! 9 !! 8 !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0 [274] => |- [275] => | {{rh}} | Register/register [276] => | colspan="7" style="background:#FFCBDB;" | funct7 [277] => | colspan="5" style="background:#dfd;" | rs2 [278] => | colspan="5" style="background:#dfd;" | rs1 [279] => | colspan="3" style="background:#FFCBDB;" | funct3 [280] => | colspan="5" style="background:#ffb7b7;" | rd [281] => | colspan="7" style="background:#FFFDD0;" | [[opcode]] [282] => |- [283] => | {{rh}} | Immediate [284] => | colspan="12" style="background:#def;" | imm[11:0] [285] => | colspan="5" style="background:#dfd;" | rs1 [286] => | colspan="3" style="background:#FFCBDB;" | funct3 [287] => | colspan="5" style="background:#ffb7b7;" | rd [288] => | colspan="7" style="background:#FFFDD0;" | opcode [289] => |- [290] => | {{rh}} | Store [291] => | colspan="7" style="background:#def;" | imm[11:5] [292] => | colspan="5" style="background:#dfd;" | rs2 [293] => | colspan="5" style="background:#dfd;" | rs1 [294] => | colspan="3" style="background:#FFCBDB;" | funct3 [295] => | colspan="5" style="background:#def;" | imm[4:0] [296] => | colspan="7" style="background:#FFFDD0;" | opcode [297] => |- [298] => | {{rh}} | Branch [299] => | style="background:#def; font-size: 75%;" | [12] [300] => | colspan="6" style="background:#def;" | imm[10:5] [301] => | colspan="5" style="background:#dfd;" | rs2 [302] => | colspan="5" style="background:#dfd;" | rs1 [303] => | colspan="3" style="background:#FFCBDB;" | funct3 [304] => | colspan="4" style="background:#def;" | imm[4:1] [305] => | style="background:#def; font-size: 75%;" | [11] [306] => | colspan="7" style="background:#FFFDD0;" | opcode [307] => |- [308] => | {{rh}} | Upper immediate [309] => | colspan="20" style="background:#def;" | imm[31:12] [310] => | colspan="5" style="background:#ffb7b7;" | rd [311] => | colspan="7" style="background:#FFFDD0;" | opcode [312] => |- [313] => | {{rh}} | Jump [314] => | style="background:#def; font-size: 75%;" | [20] [315] => | colspan="10" style="background:#def;" | imm[10:1] [316] => | style="background:#def; font-size: 75%;" | [11] [317] => | colspan="8" style="background:#def;" | imm[19:12] [318] => | colspan="5" style="background:#ffb7b7;" | rd [319] => | colspan="7" style="background:#FFFDD0;" | opcode [320] => |- [321] => | colspan="33" style="text-align:left; font-size:85%;" | [322] => * '''''opcode'' (7 bits):''' Partially specifies one of the 6 types of ''instruction formats''. [323] => * '''''funct7'' (7 bits) and ''funct3'' (3 bits):''' These two fields extend the ''opcode'' field to specify the operation to be performed. [324] => * '''''rs1'' (5 bits) and ''rs2'' (5 bits):''' Specify, by index, the first and second operand registers respectively (i.e., source registers). [325] => * '''''rd'' (5 bits):''' Specifies, by index, the destination register to which the computation result will be directed. [326] => |} [327] =>
[328] => [329] => To tame the combinations of functions that may be implemented, a nomenclature is defined to specify them in Chapter 27 of the current ratified Unprivileged ISA Specification. The instruction set base is specified first, coding for RISC-V, the register bit-width, and the variant; e.g., {{mono|RV64I}} or {{mono|RV32E}}. Then follows letters specifying implemented extensions, in the order of the above table. Each letter may be followed by a major optionally followed by "p" and a minor option number. It defaults to 0 if a minor version number is absent, and 1.0 if all of a version number is absent. Thus {{mono|RV64IMAFD}} may be written as {{mono|RV64I1p0M1p0A1p0F1p0D1p0}} or more simply as {{mono|RV64I1M1A1F1D1}}. Underscores may be used between extensions for readability, for example {{mono|RV32I2_M2_A2}}. [330] => [331] => [[File:RV32IMAC Instruction Set.svg|600px|thumb|alt=A diagram of the modular instruction set of the {{mono|RV32IMAC}} variant, showing all instructions in the base integer ISA and the extensions for Integer Multiplication and Division, Atomic Instructions, and Compressed Instructions.|The modular instruction set of the {{mono|RV32IMAC}} variant. This is a 32-bit CPU with the Base Integer ISA ({{mono|RV32I}}) and the ISA extensions for Integer Multiplication and Division ({{mono|RV32M}}), Atomic Instructions ({{mono|RV32A}}), and Compressed Instructions ({{mono|RV32C}}).]] [332] => [333] => The base, extended integer & floating-point calculations, with synchronization primitives for multi-core computing, are considered to be necessary for general-purpose computing, and thus we have the shorthand, "G". [334] => [335] => A small 32-bit computer for an embedded system might be {{mono|RV32EC}}. A large 64-bit computer might be {{mono|RV64GC}}; i.e., {{mono|RV64IMAFDCZicsr_Zifencei}}. [336] => [337] => With the growth in the number of extensions, the standard now provides for extensions to be named by a single "Z" followed by an alphabetical name and an optional version number. For example, {{mono|Zifencei}} names the instruction-fetch extension. {{mono|Zifencei2}} and {{mono|Zifencei2p0}} name version 2.0 of the same. The first letter following the "Z" by convention indicates the most closely related alphabetical extension category, {{mono|IMAFDQLCBJTPVN}}. Thus the Zam extension for misaligned atomics relates to the "A" standard extension. Unlike single character extensions, Z extensions must be separated by underscores, grouped by category and then alphabetically within each category. For example, {{mono|Zicsr_Zifencei_Zam}}. [338] => [339] => Extensions specific to supervisor privilege level are named in the same way using "S" for prefix. Extensions specific to hypervisor level are named using "H" for prefix. Machine level extensions are prefixed with the three letters "Zxm". Supervisor, hypervisor and machine level instruction set extensions are named after less privileged extensions. [340] => [341] => RISC-V developers may create their own non-standard instruction set extensions. These follow the "Z" naming convention, but with "X" as the prefix. They should be specified after all standard extensions, and if multiple non-standard extensions are listed, they should be listed alphabetically. [342] => [343] => ====Profiles and Platforms==== [344] => Profiles and Platforms for standard ISA choice lists are under discussion. [345] => {{blockquote|text=... This flexibility can be used to highly optimize a specialized design by including only the exact set of ISA features required for an application, but the same flexibility also leads to a combinatorial explosion in possible ISA choices. Profiles specify a much smaller common set of ISA choices that capture the most value for most users, and which thereby enable the software community to focus resources on building a rich software ecosystem. [346] => {{cite web |title=RISC-V Profiles |date=2022 |work=Discussion |url=https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profiles}}}} [347] => [348] => {{blockquote|text=The platform specification defines a set of platforms that specify requirements for interoperability between software and hardware. The Platform Policy defines the various terms used in this platform specification. The platform policy also provides the needed detail regarding the scope, coverage, naming, versioning, structure, life cycle and compatibility claims for the platform specification. [349] => {{cite web |author=RISC-V Platform Horizontal Subcommittee |title=RISC-V Platform Specification |date=December 2021 |id=Version 0.3-draft |url=https://github.com/riscv/riscv-platform-specs/blob/main/riscv-platform-spec.pdf}}}} [350] => [351] => ===Register sets=== [352] => {| class="wikitable" style="float:right; font-size:84%;" [353] => |+ [[Assembler mnemonics]] for RISC-V integer and floating-point registers, and their role in the first standard calling convention.{{rp|page=137}} [354] => |- [355] => ! Register
name !! Symbolic
name !! Description !! Saved by [356] => |- [357] => ! colspan="4" | 32 [[integer (computing)|integer]] registers [358] => |- [359] => | x0 ||zero|| Always zero || {{n/a|}} [360] => |- [361] => | x1 || ra || [[Return statement|Return address]] || style="background:#fffdd0;" | Caller [362] => |- [363] => | x2 || sp || [[Stack pointer]] || style="background:#def;" | Callee [364] => |- [365] => | x3 || gp || [[Global pointer]]|| {{n/a|}} [366] => |- [367] => | x4 || tp || [[Thread pointer]] || {{n/a|}} [368] => |- [369] => | x5 || t0 || Temporary / alternate return address || style="background:#fffdd0;" | Caller [370] => |- [371] => | x6–7 || t1–2 || Temporaries || style="background:#fffdd0;" | Caller [372] => |- [373] => | x8 || s0/fp || Saved register / [[frame pointer]] || style="background:#def;" | Callee [374] => |- [375] => | x9 || s1 || Saved register || style="background:#def;" | Callee [376] => |- [377] => | x10–11 || a0–1 || [[Argument (computer programming)|Function argument]]s / return values || style="background:#fffdd0;" | Caller [378] => |- [379] => | x12–17 || a2–7 || Function arguments ||style="background:#fffdd0;" | Caller [380] => |- [381] => | x18–27 || s2–11 || Saved registers || style="background:#def;" | Callee [382] => |- [383] => | x28–31 || t3–6 || Temporaries || style="background:#fffdd0;" | Caller [384] => |- [385] => ! colspan="4" | 32 [[Floating-point arithmetic|floating-point]] extension registers [386] => |- [387] => | f0–7 || ft0–7 || Floating-point temporaries || style="background:#fffdd0;" | Caller [388] => |- [389] => | f8–9 || fs0–1 || Floating-point saved registers || style="background:#def;" | Callee [390] => |- [391] => | f10–11 || fa0–1 || Floating-point arguments/return values || style="background:#fffdd0;" | Caller [392] => |- [393] => | f12–17 || fa2–7 || Floating-point arguments || style="background:#fffdd0;" | Caller [394] => |- [395] => | f18–27 || fs2–11 || Floating-point saved registers || style="background:#def;" | Callee [396] => |- [397] => | f28–31 || ft8–11 || Floating-point temporaries || style="background:#fffdd0;" | Caller [398] => |} [399] => [400] => RISC-V has 32 [[integer]] registers (or 16 in the embedded variant),{{rp|pages=13, 33}} and when the floating-point extension is implemented, an additional 32 [[Floating-point arithmetic|floating-point]] registers.{{rp|page=63}} Except for memory access instructions, instructions address only [[processor register|register]]s. [401] => [402] => The first integer register is a [[zero register]], and the remainder are general-purpose registers. A store to the zero register has no effect, and a read always provides 0. Using the zero register as a placeholder makes for a simpler instruction set. [403] => [404] => Control and status registers exist, but user-mode programs can access only those used for performance measurement and floating-point management. [405] => [406] => No instructions exist to save and restore multiple registers. Those were thought to be needless, too complex, and perhaps too slow. [407] => [408] => ===Memory access=== [409] => Like many RISC designs, RISC-V is a [[load–store architecture]]: instructions address only registers, with load and store instructions conveying data to and from memory. [410] => [411] => Most load and store instructions include a 12-bit offset and two register identifiers. One register is the base register. The other register is the destination (for a load) or the source (for a store). [412] => [413] => The offset is added to a base register to get the address.{{rp|page=24}} Forming the address as a base register plus offset allows single instructions to access data structures. For example, if the base register points to the top of a stack, single instructions can access a subroutine's local variables in the stack. Likewise the load and store instructions can access a record-style structure or a memory-mapped I/O device. Using the constant zero register as a base address allows single instructions to access memory near address zero. [414] => [415] => Memory is addressed as 8-bit bytes, with instructions being in [[little-endian]] order,{{rp|pages=9{{hyp}}10}} and with data being in the byte order defined by the execution environment interface in which code is running.{{rp|pages=3,9{{hyp}}10,24}} Words, up to the register size, can be accessed with the load and store instructions. [416] => [417] => RISC-V was originally specified as little-endian to resemble other familiar, successful computers, for example, [[x86]].{{rp|pages=9{{hyp}}10}} This also reduces a CPU's complexity and costs slightly less because it reads all sizes of words in the same order. For example, the RISC-V instruction set decodes starting at the lowest-addressed byte of the instruction. Big-endian and bi-endian variants were defined for support of legacy code bases that assume big-endianness.{{rp|pages=9{{hyp}}10}} The privileged ISA defines bits in the {{mono|mstatus}} and {{mono|mstatush}} registers that indicate and, optionally, control whether M-mode, S-mode, and U-mode memory accesses other than instruction fetches are little-endian or big-endian; those bits may be read-only, in which case the endianness of the implementation is hardwired, or may be writable.{{rp|23–24}} [418] => [419] => An execution environment interface may allow accessed memory addresses not to be aligned to their word width, but accesses to aligned addresses may be faster; for example, simple CPUs may implement unaligned accesses with slow software emulation driven from an alignment failure [[interrupt]].{{rp|pages=3,24{{hyp}}25}} [420] => [421] => Like many RISC instruction sets (and some [[complex instruction set computer]] (CISC) instruction sets, such as [[x86]] and [[IBM System/360]] and its successors through [[z/Architecture]]), RISC-V lacks address-modes that write back to the registers. For example, it does not auto-increment.{{rp|page=24}} [422] => [423] => RISC-V manages memory systems that are shared between CPUs or [[thread (computing)|threads]] by ensuring a thread of execution always sees its memory operations in the programmed order. But between threads and I/O devices, RISC-V is simplified: it doesn't guarantee the order of memory operations, except by specific instructions, such as {{code|fence}}. [424] => [425] => A {{code|fence}} instruction guarantees that the results of predecessor operations are visible to successor operations of other threads or I/O devices. {{code|fence}} can guarantee the order of combinations of both memory and memory-mapped I/O operations. E.g. it can separate memory read and write operations, without affecting I/O operations. Or, if a system can operate I/O devices in parallel with memory, {{code|fence}} doesn't force them to wait for each other. One CPU with one thread may decode {{code|fence}} as {{code|nop}}. [426] => [427] => Some RISC CPUs (such as [[MIPS architecture|MIPS]], [[PowerPC]], [[DLX]], and Berkeley's RISC-I) place 16 bits of offset in the loads and stores. They set the upper 16 bits by a ''load upper word'' instruction. This permits upper-halfword values to be set easily, without shifting bits. However, most use of the upper half-word instruction makes 32-bit constants, like addresses. RISC-V uses a [[SPARC]]-like combination of 12-bit offsets and 20-bit ''set upper'' instructions. The smaller 12-bit offset helps compact, 32-bit load and store instructions select two of 32 registers yet still have enough bits to support RISC-V's variable-length instruction coding.{{rp|page=16}} [428] => [429] => ===Immediates=== [430] => RISC-V handles 32-bit constants and addresses with instructions that set the upper 20 bits of a 32-bit register. Load upper immediate {{code|lui}} loads 20 bits into bits 31 through 12. Then a second instruction such as {{code|addi}} can set the bottom 12 bits. Small numbers or addresses can be formed by using the zero register instead of {{code|lui}}. [431] => [432] => This method is extended to permit [[position-independent code]] by adding an instruction, {{code|auipc}} that generates 20 upper address bits by adding an offset to the program counter and storing the result into a base register. This permits a program to generate 32-bit addresses that are relative to the program counter. [433] => [434] => The base register can often be used as-is with the 12-bit offsets of the loads and stores. If needed, {{code|addi}} can set the lower 12 bits of a register. In 64-bit and 128-bit ISAs,{{code|lui}} and {{code|auipc}} sign-extend the result to get the larger address.{{rp|page=37}} [435] => [436] => Some fast CPUs may interpret combinations of instructions as single ''fused'' instructions. {{code|lui}} or {{code|auipc}} are good candidates to fuse with {{code|jalr}}, {{code|addi}}, loads or stores. [437] => [438] => ===Subroutine calls, jumps, and branches=== [439] => RISC-V's subroutine call {{code|jal}} (jump and link) places its return address in a register. This is faster in many computer designs, because it saves a memory access compared to systems that push a return address directly on a stack in memory. {{code|jal}} has a 20-bit signed ([[two's complement]]) offset. The offset is multiplied by 2, then added to the PC to generate a relative address to a 32-bit instruction. If the result is not at a 32-bit address (i.e., evenly divisible by 4), the CPU may force an [[Exception handling|exception]].{{rp|pages=20–23|at=Section 2.5}} [440] => [441] => RISC-V CPUs jump to calculated addresses using a ''jump and link-register'', {{code|jalr}} instruction. {{code|jalr}} is similar to {{code|jal}}, but gets its destination address by adding a 12-bit offset to a base register. (In contrast,{{code|jal}} adds a larger 20-bit offset to the PC.) [442] => [443] => {{code|jalr}}'s bit format is like the register-relative loads and stores. Like them, {{code|jalr}} can be used with the instructions that set the upper 20 bits of a base register to make 32-bit branches, either to an absolute address (using {{code|lui}}) or a PC-relative one (using {{code|auipc}} for position-independent code). (Using a constant zero base address allows single-instruction calls to a small (the offset), fixed positive or negative address.) [444] => [445] => RISC-V recycles {{code|jal}} and {{code|jalr}} to get unconditional 20-bit PC-relative jumps and unconditional register-based 12-bit jumps. Jumps just make the linkage register 0 so that no return address is saved.{{rp|pages=20–23|at=Section 2.5}} [446] => [447] => RISC-V also recycles {{code|jalr}} to return from a subroutine: To do this, {{code|jalr}}'s base register is set to be the linkage register saved by {{code|jal}} or {{code|jalr}}. {{code|jalr}}'s offset is zero and the linkage register is zero, so that there is no offset, and no return address is saved. [448] => [449] => Like many RISC designs, in a subroutine call, a RISC-V compiler must use individual instructions to save registers to the stack at the start, and then restore these from the stack on exit. RISC-V has no ''save multiple'' or ''restore multiple'' register instructions. These were thought to make the CPU too complex, and possibly slow. This can take more code space. Designers planned to reduce code size with library routines to save and restore registers. [450] => [451] => RISC-V has no [[condition code register]] or [[carry bit]]. The designers believed that condition codes make fast CPUs more complex by forcing interactions between instructions in different stages of execution. This choice makes multiple-precision arithmetic more complex. Also, a few numerical tasks need more energy. As a result, [[Predication (computer architecture)|predication]] (the conditional execution of instructions) is not supported. The designers claim that very fast, out-of-order CPU designs do predication anyway, by doing the comparison branch and conditional code in parallel, then discarding the unused path's effects. They also claim that even in simpler CPUs, predication is less valuable than [[Branch predictor|branch prediction]], which can prevent most stalls associated with conditional branches. Code without predication is larger, with more branches, but they also claim that a [[compressed instruction set]] (such as RISC-V's set ''C'') solves that problem in most cases.{{failed verification|date=November 2021}} [452] => [453] => Instead, RISC-V has short branches that perform comparisons: equal, not-equal, less-than, unsigned less-than, greater-than or equal and unsigned greater-than or equal. Ten comparison-branch operations are implemented with only six instructions, by reversing the order of operands in the [[Assembly language|assembler]]. For example, ''branch if greater than'' can be done by ''less-than'' with a reversed order of operands.{{rp|pages=20–23|at=Section 2.5}} [454] => [455] => The comparing branches have a twelve-bit signed range, and jump relative to the PC.{{rp|pages=20–23|at=Section 2.5}} [456] => [457] => Unlike some RISC architectures, RISC-V does not include a [[branch delay slot]], a position after a branch instruction that can be filled with an instruction that is executed whether or not the branch is taken.{{rp|pages=20–23|at=Section 2.5}} RISC-V omits a branch delay slot because it complicates multicycle CPUs, superscalar CPUs, and long pipelines. Dynamic [[branch predictor]]s have succeeded well enough to reduce the need for delayed branches. [458] => [459] => On the first encounter with a branch, RISC-V CPUs should assume that a negative relative branch (i.e. the sign bit of the offset is "1") will be taken.{{rp|pages=20–23|at=Section 2.5}} This assumes that a backward branch is a loop, and provides a default direction so that simple pipelined CPUs can fill their pipeline of instructions. Other than this, RISC-V does not require [[branch prediction]], but core implementations are allowed to add it. RV32I reserves a "HINT" instruction space that presently does not contain any hints on branches;{{rp|pages=28–29|at=Section 2.9}} RV64I does the same.{{rp|pages=38–39|at=Section 5.4}} [460] => [461] => ===Arithmetic and logic sets=== [462] => RISC-V segregates math into a minimal set of [[integer]] instructions (set ''I'') with [[Arithmetic logic unit|add, subtract, shift, bitwise logic]] and comparing-branches. These can simulate most of the other RISC-V instruction sets with software. (The atomic instructions are a notable exception.) RISC-V integer instructions lacks the ''count leading zero'' and bit-field operations normally used to speed software floating-point in a pure-integer processor, However, while nominally in the bit manipulation extension, the ratified Zbb, Zba and Zbs extensions contain further integer instructions including a count leading zero instruction. [463] => [464] => The integer multiplication instructions (set ''M'') include signed and unsigned multiply and divide. Double-precision integer multiplies and divides are included, as multiplies and divides that produce the ''high word'' of the result. The ISA document recommends that implementors of CPUs and compilers ''fuse'' a standardized sequence of high and low multiply and divide instructions to one operation if possible.{{rp|pages=43{{hyp}}45}} [465] => [466] => The [[floating-point]] instructions (set ''F'') include single-precision arithmetic and also comparison-branches similar to the integer arithmetic. It requires an additional set of 32 floating-point registers. These are separate from the integer registers. The double-precision floating point instructions (set ''D'') generally assume that the floating-point registers are 64-bit (i.e., double-width), and the ''F'' subset is coordinated with the ''D'' set. A quad-precision 128-bit floating-point ISA (''Q'') is also defined.{{rp|pages=63{{hyp}}82}} RISC-V computers without floating-point can use a floating-point software library. [467] => [468] => RISC-V does not cause [[Exception handling|exceptions]] on arithmetic errors, including [[Overflow flag|overflow]],{{rp|pages=17{{hyp}}20}} underflow, subnormal, and divide by zero.{{rp|pages=44{{hyp}}45}} Instead, both integer and floating-point arithmetic produce reasonable default values, and floating-point instructions set status bits.{{rp|page=66}} Divide-by-zero can be discovered by one branch after the division.{{rp|pages=44{{hyp}}45}} The status bits can be tested by an operating system or periodic interrupt. [469] => [470] => ===Atomic memory operations=== [471] => RISC-V supports computers that share memory between multiple CPUs and [[Thread (computing)|threads]]. RISC-V's standard memory consistency model is [[release consistency]]. That is, loads and stores may generally be reordered, but some loads may be designated as ''acquire'' operations which must precede later memory accesses, and some stores may be designated as ''release'' operations which must follow earlier memory accesses.{{rp|pages=83{{hyp}}94}} [472] => [473] => The base instruction set includes minimal support in the form of a [[Fence instruction|{{code|fence}} instruction]] to enforce memory ordering.{{rp|pages=26{{hyp}}27}} Although this is sufficient ({{code|fence r, rw}} provides ''acquire'' and {{code|fence rw, w}} provides ''release''), combined operations can be more efficient.{{rp|at=Chapter 8}} [474] => [475] => The atomic memory operation extension supports two types of atomic memory operations for release consistency. First, it provides general purpose [[Load-link/store-conditional|''load-reserved'' {{code|lr}} and ''store-conditional'' {{code|sc}}]] instructions. {{code|lr}} performs a load, and tries to reserve that address for its thread. A later store-conditional {{code|sc}} to the reserved address will be performed only if the reservation is not broken by an intervening store from another source. If the store succeeds, a zero is placed in a register. If it failed, a non-zero value indicates that software needs to retry the operation. In either case, the reservation is released.{{rp|at=Chapter 8}} [476] => [477] => The second group of atomic instructions perform [[read-modify-write]] sequences: a load (which is optionally a load-acquire) to a destination register, then an operation between the loaded value and a source register, then a store of the result (which may optionally be a store-release). Making the memory barriers optional permits combining the operations. The optional operations are enabled by ''acquire'' and ''release'' bits which are present in every atomic instruction. RISC-V defines nine possible operations: swap (use source register value directly); add; bitwise and, or, and exclusive-or; and signed and unsigned minimum and maximum.{{rp|at=Chapter 8}} [478] => [479] => A system design may optimize these combined operations more than {{code|lr}} and {{code|sc}}. For example, if the destination register for a swap is the constant zero, the load may be skipped. If the value stored is unmodified since the load, the store may be skipped.{{rp|page=44}} [480] => [481] => The [[IBM System/370]] and its successors including [[z/Architecture]], and [[x86]], both implement a [[compare-and-swap]] ({{code|cas}}) instruction, which tests and conditionally updates a location in memory: if the location contains an expected old value, {{code|cas}} replaces it with a given new value; it then returns an indication of whether it made the change. However, a simple load-type instruction is usually performed before the {{code|cas}} to fetch the old value. The classic problem is that if a thread reads (loads) a value ''A'', calculates a new value ''C'', and then uses ({{code|cas}}) to replace ''A'' with ''C'', it has no way to know whether concurrent activity in another thread has replaced ''A'' with some other value ''B'' and then restored the ''A'' in between. In some algorithms (e.g., ones in which the values in memory are pointers to dynamically allocated blocks), this [[ABA problem]] can lead to incorrect results. The most common solution employs a ''double-wide {{code|cas}}'' instruction to update both the pointer and an adjacent counter; unfortunately, such an instruction requires a special instruction format to specify multiple registers, performs several reads and writes, and can have complex bus operation.{{rp|pages=48{{hyp}}49}} [482] => [483] => The {{code|lr}}/{{code|sc}} alternative is more efficient. It usually requires only one memory load, and minimizing slow memory operations is desirable. It's also exact: it controls all accesses to the memory cell, rather than just assuring a bit pattern. However, unlike {{code|cas}}, it can permit [[livelock]], in which two or more threads repeatedly cause each other's instructions to fail. RISC-V guarantees forward progress (no livelock) if the code follows rules on the timing and sequence of instructions: 1) It must use only the ''I'' subset. 2) To prevent repetitive cache misses, the code (including the retry loop) must occupy no more than 16 consecutive instructions. 3) It must include no system or fence instructions, or taken backward branches between the {{code|lr}} and {{code|sc}}. 4) The backward branch to the retry loop must be to the original sequence.{{rp|pages=48{{hyp}}49}} [484] => [485] => The specification gives an example of how to use the read-modify-write atomic instructions to lock a data structure.{{rp|page=54}} [486] => [487] => ===Compressed subset=== [488] => The standard RISC-V ISA specifies that all instructions are 32 bits. This makes for a particularly simple implementation, but like other RISC processors with 32-bit instruction encoding, results in larger code size than in instruction sets with variable-length instructions.{{rp|page=99}} [489] => [490] => To compensate, RISC-V's ''32-bit'' instructions are actually 30 bits; {{Fraction|3|4}} of the [[opcode]] space is reserved for an optional (but recommended) variable-length ''compressed'' instruction set, RVC, that includes 16-bit instructions. As in [[ARM Thumb]] and [[MIPS architecture#Application-specific extensions|MIPS16]], the compressed instructions are simply alternative encodings for a subset of the larger instructions. Unlike the ARM or MIPS compressed sets, space was reserved from the start so there is no separate operating mode. Standard and compressed instructions may be intermixed freely.{{rp|page=97}} (Extension letter is ''C''.){{rp|page=97}} [491] => [492] => Because (like Thumb-1 and MIPS16) the compressed instructions are simply alternate encodings (aliases) for a selected subset of larger instructions, the compression can be implemented in the assembler, and it is not essential for the compiler to even know about it. [493] => [494] => A prototype of RVC was tested in 2011. The prototype code was 20% smaller than an [[x86]] PC and [[MIPS architecture|MIPS]] compressed code, and 2% larger than ARM [[Thumb-2]] code. It also substantially reduced both the needed cache memory and the estimated power use of the memory system. [495] => [496] => The researcher intended to reduce the code's binary size for small computers, especially [[embedded computer]] systems. The prototype included 33 of the most frequently used instructions, recoded as compact 16-bit formats using operation codes previously reserved for the compressed set. The compression was done in the [[Assembly language|assembler]], with no changes to the compiler. Compressed instructions omitted fields that are often zero, used small immediate values or accessed subsets (16 or 8) of the registers. {{code|addi}} is very common and often compressible. [497] => [498] => Much of the difference in size compared to ARM's Thumb set occurred because RISC-V, and the prototype, have no instructions to save and restore multiple registers. Instead, the compiler generated conventional instructions that access the stack. The prototype RVC assembler then often converted these to compressed forms that were half the size. However, this still took more code space than the ARM instructions that save and restore multiple registers. The researcher proposed to modify the compiler to call library routines to save and restore registers. These routines would tend to remain in a code cache and thus run fast, though probably not as fast as a save-multiple instruction. [499] => [500] => Standard RVC requires occasional use of 32-bit instructions. Several nonstandard RVC proposals are complete, requiring no 32-bit instructions, and are said to have higher densities than standard RVC.{{cite web |last1=Brussee |first1=Rogier |title=A Complete 16-bit RVC |url=https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/SrujNcNc8RA/m/0mA-dATSBwAJ |website=Google Groups |publisher=RISC-V Foundation |access-date=18 July 2019}}{{cite web |url=https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/iK3enKGb5bw/m/cuVAq0J8EAAJ |title=Proposal: Xcondensed, [a] ... Compact ... 16 bit standalone G-ISA |last=Brussee |first=Rogier |website=RISC-V ISA Mail Server |publisher=Google Groups |access-date=10 November 2016}} Another proposal builds on these, and claims to use less coding range as well.{{cite web |last1=Phung |first1=Xan |title=Improved Xcondensed |url=https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/SrujNcNc8RA/m/DRDyXTUHAgAJ |website=Google Groups |publisher=RISC-V Foundation |access-date=18 July 2019}} [501] => [502] => ===Embedded subset=== [503] => An instruction set for the smallest ''embedded'' CPUs (set E) is reduced in other ways: Only 16 of the 32 integer registers are supported.{{rp|at=Chapter 4}} All current extensions may be used; a floating-point extension to use the integer registers for floating-point values is being considered. The privileged instruction set supports only machine mode, user mode and memory schemes that use base-and-bound address relocation. [504] => [505] => Discussion has occurred for a microcontroller profile for RISC-V, to ease development of deeply embedded systems. It centers on faster, simple C-language support for interrupts, simplified security modes and a simplified [[POSIX]] application binary interface.{{cite web |url=https://github.com/emb-riscv/specs-markdown/blob/master/README.md |title=The RISC-V Microcontroller Profile |last=Ionescu |first=Liviu |website=GitHub |access-date=5 April 2018}} [506] => [507] => Correspondents have also proposed smaller, non-standard, 16-bit ''RV16E'' ISAs: Several serious proposals would use the 16-bit ''C'' instructions with 8 × 16-bit registers. An April fools' joke proposed a very practical arrangement: Utilize 16 × 16-bit integer registers, with the standard ''EIMC'' ISAs (including 32-bit instructions.) The joke was to use [[bank switching]] when a 32-bit CPU would be clearly superior with the larger address space.{{cite mailing list |url=https://groups.google.com/a/groups.riscv.org/forum/#!msg/isa-dev/SrujNcNc8RA/uTnndiPaAgAJ |title=Proposal: RV16E |last=Barros |first=Cesar |mailing-list=RISC-V ISA Developers |date=1 April 2018 |access-date=2 April 2018}} [508] => [509] => ===Privileged instruction set=== [510] => RISC-V's ISA includes a separate privileged instruction set specification, which mostly describes three privilege levels plus an orthogonal hypervisor mode. {{As of|2021|12}}, version 1.12 is ratified by RISC-V International. [511] => [512] => Version 1.12 of the specification supports several types of computer systems: [513] => # Systems that have only ''machine mode'', perhaps for simple embedded systems, [514] => # Systems with both machine mode (for a simple [[Supervisory program|supervisor]]) and user-mode to implement relatively secure embedded systems, [515] => # Systems with machine-mode, supervisor mode (for operating system) and user-modes for typical operating systems. [516] => These correspond roughly to systems with up to four ''rings'' of privilege and security, at most: machine, hypervisor, supervisor and user. Each layer also is expected to have a thin layer of standardized supporting software that communicates to a more-privileged layer, or hardware. [517] => [518] => The ISA also includes a hypervisor mode that is [[Orthogonality (programming)|orthogonal]] to the user and supervisor modes.{{cite mailing list |url=https://groups.google.com/a/groups.riscv.org/forum/#!msg/isa-dev/SfEDPLU0NU4/WpAE_A4OBQAJ |title=Proposal for Virtualization without H mode |last=Bonzini |first=Paolo |last2=Waterman |first2=Andrew |mailing-list=RISC-V ISA Developers |access-date=24 February 2017}} The basic feature is a configuration bit that either permits supervisor-level code to access hypervisor registers, or causes an interrupt on accesses. This bit lets supervisor mode directly handle the hardware needed by a hypervisor. This simplifies the implementation of hypervisors that are hosted by an operating system. This is a popular mode to run warehouse-scale computers. To support non-hosted hypervisors, the bit can cause these accesses to interrupt to a hypervisor. The design also simplifies nesting of hypervisors, in which a hypervisor runs under a hypervisor, and if necessary it lets the kernel use hypervisor features within its own kernel code. As a result, the hypervisor form of the ISA supports five modes: machine, supervisor, user, supervisor-under-hypervisor and user-under-supervisor. [519] => [520] => The privileged instruction set specification explicitly defines ''hardware [[Thread (computing)|threads]]'', or ''harts''. Multiple hardware threads are a common practice in more-capable computers. When one thread is stalled, waiting for memory, others can often proceed. Hardware threads can help make better use of the large number of registers and execution units in fast out-of-order CPUs. Finally, hardware threads can be a simple, powerful way to handle [[interrupt]]s: No saving or restoring of registers is required, simply executing a different hardware thread. However, the only hardware thread required in a RISC-V computer is thread zero. [521] => [522] => Interrupts and exceptions are handled together. Exceptions are caused by instruction execution including illegal instructions and system calls, while interrupts are caused by external events. The existing control and status register definitions support RISC-V's error and memory exceptions, and a small number of interrupts, typically via an "advanced core local interruptor" (ACLINT).{{Cite web |title=riscv-aclint/riscv-aclint.adoc at main · riscv/riscv-aclint |url=https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc |access-date=2024-01-02 |website=GitHub |language=en}} For systems with more interrupts, the specification also defines a [[platform-level interrupt controller]] (PLIC) to coordinate large number of interrupts among multiple processors. Interrupts always start at the highest-privileged machine level, and the control registers of each level have explicit ''forwarding'' bits to route interrupts to less-privileged code. For example, the hypervisor need not include software that executes on each interrupt to forward an interrupt to an operating system. Instead, on set-up, it can set bits to forward the interrupt. [523] => [524] => Several memory systems are supported in the specification. Physical-only is suited to the simplest embedded systems. There are also four [[UNIX]]-style [[virtual memory]] systems for memory cached in mass-storage systems. The virtual memory systems support [[Memory management unit|MMU]] with four sizes, with addresses sized 32, 39, 48 and 57 bits. All virtual memory systems support 4 KiB pages, multilevel page-table trees and use very similar algorithms to walk the page table trees. All are designed for either hardware or software page-table walking. To optionally reduce the cost of page table walks, super-sized pages may be leaf pages in higher levels of a system's page table tree. SV32 is only supported on 32-bit implementations, has a two-layer page table tree and supports 4 MiB superpages. SV39 has a three level page table, and supports 2 MiB superpages and 1 GiB gigapages. SV48 is required to support SV39. It also has a 4-level page table and supports 2 MiB superpages, 1 GiB gigapages, and 512 GiB terapages. SV57 has a 5-level page table and supports 2 MiB superpages, 1 GiB gigapages, 512 GiB terapages and 256 TiB petapages. Superpages are aligned on the page boundaries for the next-lowest size of page. [525] => [526] => ===Bit manipulation=== [527] => Some bit-manipulation ISA extensions were ratified in November 2021 (Zba, Zbb, Zbc, Zbs).{{cite web |title=Bit-Manipulation ISA-extensions |date=November 2021 |publisher=RISC-V International |url=https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf}} The Zba, Zbb, and Zbs extensions are arguably extensions of the standard I integer instructions: Zba contains instructions to speed up the computation of the addresses of array elements in arrays of datatypes of size 2, 4, or 8 bytes (sh1add, sh2add, sh3add), and for 64 (and 128) bit processors when indexed with unsigned integers (add.uw, sh1add.uw, sh2add.uw, sh3add.uw and slli.uw). The Zbb instructions contains operations to count leading, trailing 0 bits or all 1 bits in a full and 32 word operations (clz, clzw, ctz, ctzw, cpop, cpopw), byte order reversion (rev8), logical instructions with negation of the second input (andn,orn, xnor), sign and zero extension (sext.b, sext.h, zext.h) that could not be provided as special cases of other instructions (andi, addiw, add.wu), min and max of (signed and unsigned) integers, (left and right) rotation of bits in a register and 32-bit words (rori,roriw, ror, rorw, rol, rolw), and a byte wise "or combine" operation which allows detection of a zero byte in a full register, useful for handling C-style null terminated strings functions. The Zbs extension allows setting, getting, clearing, and toggling individual bits in a register by their index (bseti, bset, bexti, bext, bclri, bclr, binvi,binv). [528] => [529] => The Zbc extension has instructions for "carryless multiplication", which does the multiplication of [[polynomials]] over the [[Galois field]] GF(2) (clmul, clmulh, clmulr). These are useful for cryptography and CRC checks of data integrity. [530] => [531] => Done well, a more specialised bit-manipulation subset can aid cryptographic, graphic, and mathematical operations. Further instructions that have been discussed include instructions to shift in ones, a generalized bit-reverse, shuffle and crossbar permutations, bit-field place, extract and deposit pack two words, bytes or halfwords in one register, CRC instructions, bit-matrix operations (RV64 only), conditional mix, conditional move, funnel shifts. The criteria for inclusion documented in the draft were compliant with RISC-V philosophies and ISA formats, substantial improvements in code density or speed (i.e., at least a 3-for-1 reduction in instructions), and substantial real-world applications, including preexisting compiler support. Version 0.93 of the bit-manipulation extension includes those instructions;{{cite web|editor-last1=Wolf|editor-first1=Claire|date=2021-01-10|title=RISC-V Bitmanip Extension Document Version 0.93|url=https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.93.pdf |access-date=9 March 2021|website=GitHub|publisher=RISC-V Foundation}} some of them are now in version 1.0.1 of the scalar and [[entropy source]] instructions cryptography extension.{{cite web|date=2022-02-18|title=RISC-V Cryptography Extensions Volume I Scalar & Entropy Source Instructions|website=[[GitHub]] |url=https://github.com/riscv/riscv-crypto/releases/download/v1.0.1-scalar/riscv-crypto-spec-scalar-v1.0.1.pdf|access-date=2023-01-28}} [532] => [533] => ===Packed SIMD=== [534] => Packed-SIMD instructions are widely used by commercial CPUs to inexpensively accelerate multimedia and other [[digital signal processing]]. For simple, cost-reduced RISC-V systems, the base ISA's specification proposed to use the floating-point registers' bits to perform parallel single instruction, multiple data ([[SIMD]]) sub-word arithmetic. [535] => [536] => In 2017 a vendor published a more detailed proposal to the mailing list, and this can be cited as version 0.1.{{cite web |title=Instruction Summary for a "P" ISA Proposal |url=https://docs.google.com/viewer?a=v&pid=forums&srcid=MDQwMTcyODgwMjc3MjQxMjA0NzcBMDcxOTA2MzQ5OTA0NjY2NzE0MjUBMjVTQUxGc3hCUUFKATAuMQFncm91cHMucmlzY3Yub3JnAXYy |website=Google Groups |publisher=ANDES Technologies |access-date=13 January 2020}} {{As of|2019}}, the efficiency of this proposed ISA varies from 2x to 5x a base CPU for a variety of DSP codecs.{{cite web |last1=Su |first1=Charlie |title=Comprehensive RISC-V Solutions for AIoT |url=https://riscv.org/wp-content/uploads/2018/07/Shanghai-0900-AndesV5-for-AIOT.pdf |website=RISC-V Content |publisher=RISC-V Foundation |date=30 June 2018 |access-date=28 January 2023}} The proposal lacked instruction formats and a license assignment to RISC-V International, but it was reviewed by the mailing list. Some unpopular parts of this proposal were that it added a condition code, the first in a RISC-V design, linked adjacent registers (also a first), and has a loop counter that can be difficult to implement in some microarchitectures. [537] => [538] => ===Vector set=== [539] => The proposed [[Vector processor|vector-processing]] instruction set may make the packed [[SIMD]] set obsolete. The designers hope to have enough flexibility that a CPU can implement vector instructions in a standard processor's registers. This would enable minimal implementations with similar performance to a multimedia ISA, as above. However, a true vector coprocessor could execute the same code with higher performance.{{cite web |url=https://riscv.org/wp-content/uploads/2015/06/riscv-vector-workshop-june2015.pdf |title=RISC-V Vector Extension Proposal |last1=Schmidt |first1=Colin |last2=Ou |first2=Albert |last3=Lee |first3=Yunsup |last4=Asanović |first4=Krste |author4-link=Krste Asanović |website=RISC-V |publisher=Regents of the University of California |access-date=14 March 2016}} [540] => [541] => {{As of|2021|09|19}}, the vector extension is at version 1.0.{{cite web | url=https://github.com/riscv/riscv-v-spec/releases/tag/v1.0 | title=Release Vector Extension 1.0, frozen for public review · riscv/Riscv-v-spec | website=[[GitHub]]}} It is a conservative, flexible design of a general-purpose mixed-precision vector processor, suitable to execute [[compute kernel]]s. Code would port easily to CPUs with differing vector lengths, ideally without recompiling. [542] => [543] => In contrast, short-vector SIMD extensions are less convenient. These are used in [[x86]], ARM and [[PA-RISC]]. In these, a change in word-width forces a change to the instruction set to expand the vector registers (in the case of x86, from 64-bit [[MMX (instruction set)|MMX]] registers to 128-bit [[Streaming SIMD Extensions]] (SSE), to 256-bit [[Advanced Vector Extensions]] (AVX), and [[AVX-512]]). The result is a growing instruction set, and a need to port working code to the new instructions. [544] => [545] => In the RISC-V vector ISA, rather than fix the vector length in the architecture, instructions ({{code|vsetvli}}, {{code|vsetivli}}, and {{code|vsetvl}}) are available which take a requested size and sets the vector length to the minimum of the hardware limit and the requested size. So, the RISC-V proposal is more like a [[Cray-1|Cray]]'s long-vector design or ARM's Scalable Vector Extension. That is, each vector in up to 32 vectors is the same length.{{rp|25}} [546] => [547] => The application specifies the total vector width it requires, and the processor determines the vector length it can provide with available on-chip resources. This takes the form of an instruction ({{code|vsetcfg}}) with four immediate operands, specifying the number of vector registers of each available width needed. The total must be no more than the addressable limit of 32, but may be less if the application does not require them all. The vector length is limited by the available on-chip storage divided by the number of bytes of storage needed for each entry. (Added hardware limits may also exist, which in turn may permit SIMD-style implementations.) [548] => [549] => Outside of vector loops, the application can zero the number of requested vector registers, saving the operating system the work of preserving them on [[context switch]]es. [550] => [551] => The vector length is not only architecturally variable, but designed to vary at run time also. To achieve this flexibility, the instruction set is likely to use variable-width data paths and variable-type operations using polymorphic overloading. The plan is that these can reduce the size and complexity of the ISA and compiler. [552] => [553] => Recent experimental vector processors with variable-width data paths also show profitable increases in operations per: second (speed), area (lower cost), and watt (longer battery life).{{cite web |url=http://www.eecs.berkeley.edu/~yunsup/papers/hwacha-mvp-prism2014.pdf |title=A Case for MVPs: Mixed-Precision Vector Processors |last1=Ou |first1=Albert |last2=Nguyen |first2=Quan |last3=Lee |first3=Yunsup |last4=Asanović |first4=Krste |author4-link=Krste Asanović |website=UC Berkeley EECS |publisher=Regents of the University of California |access-date=14 March 2016 |archive-url=https://web.archive.org/web/20160315090613/http://www.eecs.berkeley.edu/~yunsup/papers/hwacha-mvp-prism2014.pdf |archive-date=15 March 2016 |url-status=dead}} [554] => [555] => Unlike a typical modern [[graphics processing unit]], there are no plans to provide special hardware to support [[branch predication]]. Instead, lower cost compiler-based predication will be used.{{cite web |url=http://www.eecs.berkeley.edu/~yunsup/papers/predication-micro2014.pdf |title=Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures |last1=Lee |first1=Yunsup |last2=Grover |first2=Vinod |last3=Krashinsky |first3=Ronny |last4=Stephenson |first4=Mark |last5=Keckler |first5=Stephen W. |last6=Asanović |first6=Krste |author6-link=Krste Asanović |website=Berkeley's EECS Site |publisher=Regents of the University of California |access-date=14 March 2016 |archive-url=https://web.archive.org/web/20160315090618/http://www.eecs.berkeley.edu/~yunsup/papers/predication-micro2014.pdf |archive-date=15 March 2016 |url-status=dead}} [556] => [557] => ===External debug system=== [558] => There is a preliminary specification for RISC-V's hardware-assisted [[debugger]]. The debugger will use a transport system such as Joint Test Action Group ([[JTAG]]) or Universal Serial Bus ([[USB]]) to access debug registers. A standard hardware debug interface may support either a ''standardized abstract interface'' or ''instruction feeding''.{{cite web |url=https://docs.google.com/presentation/d/1x53gVvPrDWEYq3omqLUpJBHU594zidDvoIg42mUzHvM/edit#slide=id.p |title=RISC-V Run Control Debug |last1=Bradbury |first1=Alex |last2=Wallentowitz |first2=Stefan |website=Google Docs |publisher=RISC-V Foundation |access-date=20 January 2017}}{{cite web |url=https://groups.google.com/a/groups.riscv.org/forum/#!topic/debug/FDmZUk7YCNw |title=RISC-V Debug Group > poll results |last=Newsome |first=Tim |website=Google Groups, RISC-V Debug Group |publisher=RISC-V Foundation |access-date=20 January 2017}} [559] => [560] => {{As of|2017|01}}, the exact form of the ''abstract interface'' remains undefined, but proposals include a memory mapped system with standardized addresses for the registers of debug devices or a command register and a data register accessible to the communication system. Correspondents claim that similar systems are used by [[Freescale]]'s [[background debug mode interface]] (BDM) for some CPUs, [[ARM architecture|ARM]], [[OpenRISC]], and [[Aeroflex]]'s [[LEON]]. [561] => [562] => In ''instruction feeding'', the CPU will process a debug exception to execute individual instructions written to a register. This may be supplemented with a data-passing register and a module to directly access the memory. Instruction feeding lets the debugger access the computer exactly as software would. It also minimizes changes in the CPU, and adapts to many types of CPU. This was said to be especially apt for RISC-V because it is designed explicitly for many types of computers. The data-passing register allows a debugger to write a data-movement loop to RAM, and then execute the loop to move data into or out of the computer at a speed near the maximum speed of the debug system's data channel. Correspondents say that similar systems are used by [[MIPS Technologies]] [[MIPS architecture|MIPS]], [[Intel Quark]], [[Tensilica]]'s [[Xtensa]], and for [[Freescale]] [[Power ISA]] CPUs' [[background debug mode interface]] (BDM). [563] => [564] => A vendor proposed a hardware trace subsystem for standardization, donated a conforming design, and initiated a review.{{cite web |last1=McGooganus |title=riscv-trace-spec |url=https://github.com/riscv/riscv-trace-spec |website=GitHub |access-date=13 January 2020}}{{cite web |last1=Dahad |first1=Nitin |title=UltraSoC Tackles RISC-V Support Challenge by Donating Trace Encoder |url=https://www.eetimes.com/ultrasoc-tackles-risc-v-support-challenge-by-donating-trace-encoder/ |website=EE Times |publisher=Aspencore |access-date=13 January 2020}} The proposal is for a hardware module that can trace code execution on most RISC-V CPUs. To reduce the data rate, and permit simpler or less-expensive paths for the trace data, the proposal does not generate trace data that can be calculated from a binary image of the code. It sends only data that indicates "uninferrable" paths through the program, such as which conditional branches are taken. To reduce the data rates, branches that can be calculated, such as unconditional branches, are not traced. The proposed interface between the module and the control unit is a logic signal for each uninferrable type of instruction. Addresses and other data are to be provided in a specialized bus attached to appropriate data sources in a CPU. The data structure sent to an external trace unit is a series of short messages with the needed data. The details of the data channel are intentionally not described in the proposal, because several are likely to make sense. [565] => [566] => ==Implementations== [567] => The RISC-V organization maintains a list of RISC-V CPU and SoC implementations.{{cite web |title=RISC-V Cores and SoC Overview |url=https://github.com/riscv/riscv-cores-list |publisher=RISC-V |access-date=5 October 2019 |date=25 September 2019}} [568] => [569] => ===Existing=== [570] => Existing proprietary implementations include: [571] => [572] => * [[Allwinner Technology]] has implemented the XuanTie C906 CPU into their D1 Application Processor.{{cite web| url=https://www.allwinnertech.com/index.php?c=product&a=index&id=97 | title=D1 | access-date=2021-09-30}} [573] => * [[Andes Technology|Andes Technology Corporation]], a Founding Premier member of RISC-V International.{{cite web |url=https://riscv.org/members/ |title=RISC-V International Members |website=RISC-V International |access-date=2021-01-22}} Its RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, vector, superscalar, and/or multicore capabilities. [574] => * Bouffalo Lab has a series of MCUs based on RISC-V (RV32IMACF, BL60x/BL70x series).{{Cite web|url=https://www.eetimes.com/at-ces2022-bouffalo-shows-its-matter-turnkey-solution/|title=At CES2022 Bouffalo Shows its Matter Turnkey Solution|website=www.eetimes.com|access-date=2022-01-20}} [575] => * CloudBEAR is a processor IP company that develops its own RISC-V cores for a range of applications.{{cite web |url=https://cloudbear.ru/ |title=CloudBEAR|access-date=2018-10-16}} [576] => * [[Codasip]], a founding member of RISC-V International, has developed a range of low-power embedded, high-performance embedded and application processor cores.{{Citation|title=riscv/riscv-cores-list|date=2021-02-06|url=https://github.com/riscv/riscv-cores-list|publisher=RISC-V|access-date=2021-02-09}}{{Cite web|title=Codasip announces RISC-V processor cores providing multi-core and SIMD capabilities|url=https://www.newelectronics.co.uk/electronics-news/codasip-announces-risc-v-processor-cores-providing-multi-core-and-simd-capabilities/232807/|access-date=2021-02-09|website=www.newelectronics.co.uk|archive-date=23 December 2020|archive-url=https://web.archive.org/web/20201223193035/https://www.newelectronics.co.uk/electronics-news/codasip-announces-risc-v-processor-cores-providing-multi-core-and-simd-capabilities/232807/|url-status=dead}} [577] => * Cortus, an original founding Platinum member of the RISC-V foundation and the RISC-V International, has several RISC-V implementations. Cortus offers ASIC design services using its large IP portfolio including RISC-V 32/64-bit processors from low-end to very high performance RISC-V OoO processors, digital, analog, RF, security and a complete IDE/toolchain/debug eco-system. [578] => * Espressif added a RISC-V ULP coprocessor to their [[ESP32-S2]] microcontroller.{{cite book |chapter=3.6.2 Ultra-Low-Power Co-Processor |url=https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf |title=ESP32-S2 Family Datasheet V1.1 |date=2020 |publisher=Espressif Systems |access-date=2020-06-09}} In November 2020 Espressif announced their ESP32-C3, a single-core, 32-bit, RISC-V (RV32IMC) based MCU.{{cite web |url=https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf |title=ESP32-C3 Family Datasheet V0.4 |date=2020 |publisher=Espressif Systems |access-date=2020-12-27}} [579] => *{{cite press release |date=November 27, 2020 |title=Introducing ESP32-C3 |url=https://www.espressif.com/en/news/ESP32_C3 |website=Espressif}} [580] => * [[Fraunhofer Society|Fraunhofer]] IPMS was the first organization to develop a RISC-V core that can meet functional safety requirements. The IP Core EMSA5 is a 32-bit processor with a five-stage pipeline and is available as a general purpose variant (EMSA5-GP) and as a safety variant (EMSA5-FS) that can meet an [[ISO 26262]] [[Automotive Safety Integrity Level]]-D standard.{{Cite web |last=Manners |first=David |date=2021-06-08 |title=Fraunhofer licensing fault-tolerant RISC core for safety-critical applications |url=https://www.electronicsweekly.com/news/business/fraunhofer-designs-fault-tolerant-risc-core-safety-critical-applications-2021-06/ |access-date=2022-04-13 |website=Electronics Weekly |language=en}} [581] => * [[GigaDevice]] has a series of MCUs based on RISC-V (RV32IMAC, GD32V series),{{Cite web|url=https://www.gigadevice.com/press-release/gigadevice-unveils-the-gd32v-series-with-risc-v-core-in-a-brand-new-32bit-general-purpose-microcontroller/|title=GigaDevice Unveils The GD32V Series With RISC-V Core in a Brand New 32-bit General Purpose Microcontroller|website=www.gigadevice.com|date=23 August 2019|access-date=2019-08-29|archive-date=29 August 2019|archive-url=https://web.archive.org/web/20190829184033/https://www.gigadevice.com/press-release/gigadevice-unveils-the-gd32v-series-with-risc-v-core-in-a-brand-new-32bit-general-purpose-microcontroller/|url-status=dead}} with one of them used on the Longan Nano board produced by a Chinese electronic company ''Sipeed''.{{Cite web|url=https://www.seeedstudio.com/Sipeed-Longan-Nano-RISC-V-GD32VF103CBT6-Development-Board-p-4205.html|title=Sipeed Longan Nano - RISC-V GD32VF103CBT6 Development Board|website=www.seeedstudio.com|language=en|access-date=2019-08-29}} [582] => * [[Google]] has developed the [[Titan M|Titan M2]] security module for the [[Pixel 6]] and [[Pixel 7]]{{Cite web |last1=Kleidermacher |first1=Dave |last2=Seed |first2=Jesse |last3=Barbello |first3=Brandon |date=2021-10-27 |title=Pixel 6: Setting a new standard for mobile security |url=https://security.googleblog.com/2021/10/pixel-6-setting-new-standard-for-mobile.html |archive-url=https://web.archive.org/web/20211027171805/https://security.googleblog.com/2021/10/pixel-6-setting-new-standard-for-mobile.html |archive-date=2021-10-27 |access-date=2023-02-12 |website=Google Security Blog}} [583] => * GreenWaves Technologies announced the availability of GAP8, a 32-bit 1 controller plus 8 compute cores, 32-bit SoC (RV32IMC) and developer board in February 2018. Their GAPuino GAP8 development board started shipping in May 2018.{{cite web |url=https://www.cnx-software.com/2018/02/27/greenwaves-gap8-is-a-low-power-risc-v-iot-processor-optimized-for-artificial-intelligence-applications/ |title=GreenWaves GAP8 is a Low Power RISC-V IoT Processor Optimized for Artificial Intelligence Applications |website=CNXSoft: Embedded Systems News |access-date=2018-03-04|date=27 February 2018 }}{{Cite news |url=https://www.eetimes.com/document.asp?doc_id=1333003 |title=AI Comes to Sensing Devices |last=Yoshida |first=Junko |work=EE Times |date=2018-02-26 |access-date=2018-07-10}}{{cite press release |url=https://greenwaves-technologies.com/en/gap8-software-development-kit-and-gapuino-development-board/ |title=GreenWaves Technologies Announces Availability of GAP8 Software Development Kit and GAPuino Development Board |date=2018-05-22}} [584] => * [[Imagination Technologies]] RTXM-2200{{Cite web |title=IMG RTXM-2200 CPU |url=https://www.imaginationtech.com/products/cpu/img-rtxm-2200/ |access-date=2023-09-30 |website=Imagination |language=en-GB}} is the first core from their Catapult range. It’s a real-time, deterministic, 32-bit embedded CPU [585] => * [https://www.fpga-cores.com/instant-soc/ Instant SoC] RISC-V cores from FPGA cores. [[System on a chip|System on chip]], including RISC-V cores, defined by C++. [586] => * Micro Magic Inc. announced the world's fastest 64-bit RISC-V core achieving 5 GHz and 13,000 CoreMarks in October 2020. [587] => * [[MIPS Technologies|MIPS]] pivoted to developing RISC-V cores in 2021. It rolled out its first implementation eVocore P8700 in December 2022.{{cite web |url=https://www.eejournal.com/article/mips-rolls-out-its-first-risc-v-processor-core-its-a-big-un/ |title=MIPS Rolls Out Its First RISC-V Processor Core – It's a Big 'Un |date=9 January 2023 |last=Leibson |first=Steven |website=EEJournal}}{{cite web |url=https://www.theregister.com/2022/05/11/mips_riscv_chips/ |title=MIPS discloses first RISC-V chips coming in Q4 2022 |date=11 May 2022 |last=Robinson |first=Dan |website=The Register}} [588] => * [[Seagate Technology|Seagate]], in December 2020 announced that it had developed two RISC-V general-purpose cores for use in upcoming controllers for its storage devices.{{cite web |url=https://www.tomshardware.com/news/seagate-develops-risc-v-cores |title=Seagate Develops Own RISC-V Cores for Storage Controllers |last1=Shilov |first1=Anton |date=9 December 2020 |work=[[Tom's Hardware]]}} [589] => * [[SiFive]], a company established specifically for developing RISC-V hardware, has processor models released in 2017.{{cite web |url=https://www.sifive.com/products/hifive1/ |title=HiFive1 |website=SiFive |access-date=2018-07-10 |archive-date=26 February 2017 |archive-url=https://web.archive.org/web/20170226212908/https://www.sifive.com/products/hifive1/ |url-status=dead }}{{cite web |url=https://www.crowdsupply.com/sifive/hifive1/ |title=Hi-Five1: Open-source Arduino-Compatible Development Kit |author=SiFive |website=Crowd Supply |access-date=2 December 2016}} These include a quad-core, 64-bit (RV64GC) [[system on a chip]] (SoC) capable of running general-purpose operating systems such as Linux.{{cite web |url=https://www.sifive.com/chip-designer#fu540 |title=FU540 SoC CPU |website=SiFive |access-date=2018-10-24 |ref=FU540 |archive-url=https://web.archive.org/web/20181005225710/https://www.sifive.com/chip-designer#fu540 |archive-date=5 October 2018 |url-status=dead}} [590] => * StarFive, an offshoot of SiFive based in China, offers two RISC-V implementations{{snd}}one for big data applications and the other for computational storage.{{cite news |last=Horwitz |first=Josh |date=23 March 2023 |title=Chinese search giant Baidu invests in RISC-V chip technology startup StarFive |url=https://www.reuters.com/technology/chinese-search-giant-baidu-invests-risc-v-chip-technology-startup-starfive-2023-03-23/ |publisher=[[Reuters]]}}{{cite web |last=Sharwood |first=Simon |date=27 March 2023 |title=Chinese web giant Baidu backs RISC-V for the datacenter |url=https://www.theregister.com/2023/03/27/baidu_starfive_datacenter_promotion_investment/ |website=[[The Register]]}} [591] => * Syntacore,{{cite web |url=https://syntacore.com/ |title=Syntacore |access-date=2018-12-11}} a founding member of RISC-V International and one of the first commercial RISC-V IP vendors, develops and licenses family of RISC-V IP since 2015. {{As of|2018}}, product line includes eight 32- and 64-bit cores, including open-source SCR1 MCU core (RV32I/E[MC]).{{cite web |title=SCR1 is a high-quality open-source RISC-V MCU core in Verilog |url=https://github.com/syntacore/scr1 |website=GitHub |publisher=Syntacore |access-date=2020-01-13}} First commercial SoCs, based on the Syntacore IP were demonstrated in 2016.{{cite web |url=https://riscv.org/proceedings/2016/12/5th-risc-v-workshop-proceedings/ |title=RISC-V workshop proceedings |access-date=2023-01-28|date=11 December 2016 }} [592] => * WinChipHead (WCH), a Chinese semiconductor manufacturer of popular and inexpensive USB chips such as CH340 and ARM microcontrollers{{cite web |url=https://www.wch-ic.com/about_us.html|title=WinChipHead (WCH)}} introduced a simple, inexpensive RISC-V microcontroller line CH32Vxxx, headed by US$0.10 CH32V003.{{cite web |url=https://www.wch-ic.com/products/CH32V003.html|title=CH32V003 |website=WCH-IC |access-date=2023-07-10}}{{cite web |url=https://www.eevblog.com/forum/blog/eevblog-1524-the-10-cent-risc-v-processor-ch32v003/|title=the-10-cent-risc-v-processor-ch32v003|website=EEvblog |access-date=2023-07-10}} [593] => * Codasip and UltraSoC have developed fully supported intellectual property for RISC-V embedded SOCs that combine Codasip's RISC-V cores and other IP with UltraSoC's debug, optimization and analytics.{{cite web|last=Manners|first=David|date=23 November 2016|title=Codasip and UltraSoC Combine on RISC-V|url=http://www.electronicsweekly.com/news/business/codasip-ultrasoc-combine-risc-v-2016-11/|access-date=23 November 2016|website=Electronics Weekly|publisher=Metropolis International Group, Ltd.}} [594] => * As of 2020, the Indian defence and strategic sector started using the 64-bit RISC-V based 100-350 MHz [[SHAKTI - Microprocessor & Microcontroller#Risecreek|Risecreek]] processor{{Citation needed|date=December 2020}} developed by [[IIT Madras|IIT-Madras]] which is fabricated by [[Intel]] with 22 nm [[FinFET]] process.{{Cite news|last=Desikan|first=Shubashree|date=2018-08-06|title=IIT-Madras powers up a desi chip|language=en-IN|work=The Hindu|url=https://www.thehindu.com/sci-tech/technology/iit-madras-powers-up-a-desi-chip/article24609946.ece|access-date=2020-09-25|url-access=subscription|issn=0971-751X}}{{Cite web|title=Meet India's Atmanirbhar Microprocessor chip 'Moushik', meant for IoT devices|url=https://www.wionews.com/india-news/meet-indias-atmanirbhar-microprocessor-chip-moushik-meant-for-iot-devices-329966|access-date=2020-09-25|website=WION|language=en}} [595] => * RIES v3.0d development boards are the first to use DIR-V VEGA RISC-V processors. It contains the VEGA ET1031, a 32-bit RISC-V CPU with three [[UART]] serial ports, four [[Serial Peripheral Interface]] ports, two megabytes of [[flash memory]], 256KB of [[Static random-access memory|SRAM]], and three 32-bit timers. It operates at 100 MHz. It is advised for usage in wearables, toys, small IoT devices, and sensors by [[C-DAC]] in Indian market.{{Cite web |last=Dobberstein |first=Laura |title=India’s homebrew RISC-V CPU debuts in cheap dev board |url=https://www.theregister.com/2024/02/26/asia_tech_news_roundup/ |access-date=2024-03-06 |website=The Register |language=en}} [596] => [597] => ===In development=== [598] => * ASTC developed a RISC-V CPU for embedded ICs.{{cite mailing list |last=Ashenden |first=Peter |date=9 November 2016 |title=Re: [isa-dev] RISC V ISA for embedded systems |quote=At ASTC (www.astc-design.com), we have an implementation of RV32EC as a synthesizable IP core intended for small embedded applications, such as smart sensors and IoT. |url=https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/j2okI7akT74/BQdUwjMRAgAJ |mailing-list=RISC-V ISA Developers [599] => |access-date=10 November 2016}} [600] => * [[Centre for Development of Advanced Computing]] (C-DAC) in India is developing a single core 32-bit in-order, a single core 64-bit in-order and three out-of-order single, dual and quad-core RISC-V processor under [[VEGA Microprocessors]] series.{{Cite web|url=https://timesofindia.indiatimes.com/home/education/news/c-dac-announces-tech-conclave-2019/articleshow/68650294.cms|title=C-DAC announces Tech Conclave 2019|website=The Times of India|access-date=2019-04-12|archive-url=https://web.archive.org/web/20190517221350/https://timesofindia.indiatimes.com/home/education/news/c-dac-announces-tech-conclave-2019/articleshow/68650294.cms|archive-date=17 May 2019|url-status=dead}}{{Cite web|last=Sharwood|first=Simon|date=19 August 2020|title=India selects RISC-V for semiconductor self-sufficiency contest: Use these homegrown cores to build kit|url=https://www.theregister.com/2020/08/19/india_microprocessor_challenge_risc_v/ |access-date=2021-07-09|website=The Register|language=en}}{{Cite web|date=9 July 2021|title=VEGA MICROPROCESSORS|url=https://vegaprocessors.in/vega.html |access-date=9 July 2021|website=Vega Processor - CDAC|archive-url=https://web.archive.org/web/20210709185343/https://vegaprocessors.in/vega.html|archive-date=9 July 2021|url-status=dead}} [601] => * [[Cobham plc|Cobham Gaisler]] NOEL-V 64-bit.{{cite web |url=https://www.gaisler.com/index.php/products/processors/noel-v |title=NOEL-V Processor |website=Cobham Gaisler |access-date=14 January 2020}} [602] => * [[Computer Laboratory, University of Cambridge]], in collaboration with the [[FreeBSD]] Project, has ported that operating system to 64-bit RISC-V to use as a hardware-software research platform. [603] => * Esperanto Technologies announced that they are developing three RISC-V based processors: the ''ET-Maxion'' high-performance core, ''ET-Minion'' energy-efficient core, and ''ET-Graphics'' graphics processor.{{cite web |url=https://fuse.wikichip.org/news/686/esperanto-exits-stealth-mode-aims-at-ai-with-a-4096-core-7nm-risc-v-monster/ |title=Esperanto exits stealth mode, aims at AI with a 4,096 core 7nm RISC-V monster |website=wikichip.org |access-date=2 January 2018|date=January 2018 }} [604] => ** Esperanto ET-SoC-1, a 200 TOPS "kilocore" supercomputer on a chip, with 1088 small 64-bit in-order ET-Minion cores with tensor/vector units and 4 big 64-bit out-of-order ET-Maxion cores{{Cite web|url=https://www.servethehome.com/esperanto-et-soc-1-1092-risc-v-ai-accelerator-solution-at-hot-chips-33|title=Esperanto ET-SoC-1 1092 RISC-V AI Accelerator Solution at Hot Chips 33|date=24 August 2021}} [605] => * [[ETH Zurich]] and the [[University of Bologna]] have cooperatively developed the open-source RISC-V PULPino processor{{cite web |url=https://github.com/pulp-platform/pulpino |title=PULPino GitHub project |website=GitHub |access-date=2 February 2018}} as part of the Parallel Ultra-Low Power (PULP) project for energy-efficient IoT computing.{{cite web |url=https://pulp-platform.org/ |title=PULP Platform |website=PULP Platform |access-date=2 February 2018}} [606] => * [[European Processor Initiative]] (EPI), RISC-V Accelerator Stream.{{cite web |url=https://www.european-processor-initiative.eu/accelerator/ |title=Accelerator Stream |website=European Processor Initiative (EPI) |access-date=22 February 2020}}{{cite web |url=https://riscv.org/news/2019/08/how-the-european-processor-initiative-is-leveraging-risc-v-for-the-future-of-supercomputing/ |title=How the European Processor Initiative is Leveraging RISC-V for the Future of Supercomputing |work=RISC-V International News |publisher=RISC-V International |first=Calista |last=Redmond |date=28 January 2023}}[[File:RISC-V EPAC.png|thumb|Illustration of [[European Processor Initiative|EPI]]'s first working RISC-V chip sample in 2021.]] [607] => * Reconfigurable Intelligent Systems Engineering Group (RISE) of [[IIT Madras|IIT-Madras]] is developing six [[SHAKTI - Microprocessor & Microcontroller|Shakti]] series RISC-V open-source CPU designs for six distinct uses, from a small [[32-bit CPU]] for the [[Internet of things]] (IoT) to large, [[64-bit CPU]]s designed for warehouse-scale computers such as [[server farm]]s based on [[RapidIO]] and [[Hybrid Memory Cube]] technologies.{{Cite web|last=Halfacree|first=Gareth|date=10 June 2021|title=RISC-V boffins lay out a plan for bringing the architecture to high-performance computing|url=https://www.theregister.com/2021/06/10/riscv_hpc/ |access-date=2021-07-09|website=The Register|language=en}} 32-bit Moushik successfully booted by RISE for the application of credit cards, [[electronic voting machine]]s (EVMs), surveillance cameras, safe locks, personalized health management systems.{{Cite web|date=24 September 2020|title=IIT Madras Develops and Boots up MOUSHIK Microprocessor for IoT Devices|url=https://www.iitm.ac.in/happenings/press-releases-and-coverages/iit-madras-develops-and-boots-moushik-microprocessor-iot |access-date=2021-07-09|website=IIT Madras}} [608] => * [[lowRISC]] is a non profit project to implement a fully [[open-source hardware]] [[system on a chip]] (SoC) based on the 64-bit RISC-V ISA. [609] => * [[Nvidia]] plans to use RISC-V to replace their Falcon processor on their [[GeForce]] graphics cards.{{cite AV media |first=Joe |last=Xie |date=July 2016 |title=NVIDIA RISC V Evaluation Story |work=4th RISC-V Workshop |url=https://www.youtube.com/watch?v=gg1lISJfJI0 | archive-url=https://ghostarchive.org/varchive/youtube/20211113/gg1lISJfJI0| archive-date=2021-11-13 | url-status=live|publisher=Youtube}}{{cbignore}} [610] => *RV64X consortium is working on a set of graphics extensions to RISC-V and has announced that they are developing an open source RISC-V core with a GPU unit.{{Cite web|last=|first=|date=|title=RV64X: A Free, Open Source GPU for RISC-V|url=https://www.eetimes.com/rv64x-a-free-open-source-gpu-for-risc-v/ |access-date=9 February 2021|website=EETimes}} [611] => * [[SiFive]] announced their first RISC-V [[Out-of-order execution#Out-of-order processors|out-of-order]] high performance CPU core, the U8 Series Processor IP.{{cite web|url=https://www.anandtech.com/show/15036/sifive-announces-first-riscv-ooo-cpu-core-the-u8series-processor-ip|title=SiFive Announces First RISC-V OoO CPU Core: The U8-Series Processor IP|first=Andrei|last=Frumusanu|date=October 30, 2019|website=[[Anandtech]]}} [612] => * Ventana revealed they are developing high performance RISC-V CPU IP and chiplet technology targeting data center applications.{{cite journal|last=Gwennap|first=Linley|title=Ventana Develops RISC-V Chiplet|journal=[[Microprocessor Report]]|date=December 13, 2021}}{{cite web|url=https://www.eetimes.com/risc-v-chiplet-startup-raises-38m-targets-data-center-compute/|title=RISC-V Chiplet Startup Raises $38m, Targets Data Center Compute|first=Nitin|last=Dahad|date=September 6, 2021|website=[[EE Times]]}} [613] => [614] => ===Open source=== [615] => Many open-sourced RISC-V CPU designs exist, including: [616] => * The Berkeley CPUs. These are implemented in a unique hardware design language, [[Chisel (programming language)|Chisel]], and some are named for famous train engines: [617] => ** 64-bit Rocket.{{cite web |url=https://github.com/ucb-bar/rocket-chip |title=rocket-chip |last=Asanović |first=Krste |author-link=Krste Asanović |display-authors=etal|website=GitHub |publisher=RISC-V International |access-date=11 November 2016}} Rocket may suit compact, low-power intermediate computers such as personal devices. Named for [[Stephenson's Rocket|Stephenson's ''Rocket'']]. [618] => ** The [[64-bit computing|64-bit]] Berkeley Out of Order Machine (BOOM).{{cite web |url=https://github.com/riscv-boom/riscv-boom |last=Celio |first=Christopher |title=riscv-boom |website=GitHub |publisher=Regents of the University of California |access-date=29 March 2020}} The Berkeley Out-of-Order Machine (BOOM) is a synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language. BOOM uses much of the infrastructure created for Rocket, and may be usable for personal, supercomputer, and warehouse-scale computers. [619] => ** Five [[32-bit computing|32-bit]] Sodor CPU designs from Berkeley, designed for student projects. [[Sodor (fictional island)|Sodor]] is the fictional island of trains in children's stories about [[Thomas the Tank Engine]]. [620] => * PicoRV32 by {{Visible anchor|Claire Wolf}},{{cite web |last1=Wolf |first1=Claire |title=PicoRV32 - A Size-Optimized RISC-V CPU |url=https://github.com/cliffordwolf/picorv32 |website=GitHub |access-date=27 February 2020}} a 32-bit [[microcontroller unit]] (MCU) class RV32IMC implementation in [[Verilog]]. [621] => * SCR1 from Syntacore, a 32-bit microcontroller unit (MCU) class RV32IMC implementation in [[Verilog]]. [622] => * MIPT-MIPS{{Cite web |title=MIPT-MIPS: Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs |url=https://github.com/MIPT-ILab/mipt-mips/ |website=GitHub}} by MIPT-ILab ([[Moscow Institute of Physics and Technology|MIPT]] Lab for CPU Technologies created with help of [[Intel]]). MIPT-MIPS is a cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs. It measures ''performance'' of program running on CPU. Among key features are: compatibility with interactive MARS system calls,{{Cite web |title=MIPS syscall functions available in MARS |url=https://courses.missouristate.edu/KenVollmar/mars/Help/SyscallHelp.html |access-date=2023-05-28 |website=courses.missouristate.edu}} interactive simulation with [[GNU Debugger|GDB]], configurable [[Branch predictor|branch prediction unit]] with several prediction algorithms and instruction cache and interstage data bypassing. Implementation in C++. [623] => * SERV{{cite web |last1=Kindgren |first1=Olof |title=SERV - The serial RISC-V CPU |url=https://github.com/olofk/serv |website=GitHub |access-date=25 September 2023}} by Olof Kindgren, a physically small, validated bit-serial RV32I core in [[Verilog]], is the world's smallest RISC-V CPU. It is integrated with both the LiteX and FuseSoC SoC construction systems. An FPGA implementation{{cite web |last1=Kindgren |first1=Olof |date=29 December 2022 |title=SERV: 32-bit is the New 8-bit |url=https://www.award-winning.me/serv-32-bit-is-the-new-8-bit/ |archive-url= |archive-date= |access-date=25 September 2023 |website=YouTube |publisher=RISC-V Foundation |format=Video, 2:38}}{{cbignore}} was 125 [[Lookup table#Hardware LUTs|lookup tables]] (LUTs) and 164 [[flip-flop (electronics)|flip-flops]], running at 1.5 [[million instructions per second|MIPS]], In a 130 nm-node ASIC, it was 2.1kGE and a high-end FPGA could hold 10,000 cores.{{cite web |last1=Halfacree |first1=Gareth |date=14 June 2022 |title=CoreScore Benchmark Sees New Record with 10,000 RISC-V Cores on One FPGA |url=https://fossi-foundation.org/blog/2022-06-14-ecl51#corescore-benchmark-sees-new-record-with-10000-risc-v-cores-on-one-fpga |access-date=25 September 2023 |website=fossi-foundation.org |publisher=FOSSi Foundation}} [624] => * PULPino (Riscy and Zero-Riscy) from ETH Zürich / University of Bologna.{{cite web |url=https://www.pulp-platform.org/ |title=PULP: Parallel Ultra Low Power |last=Traber |first=Andreas |display-authors=etal|publisher=ETH Zurich, University of Bologna |access-date=5 August 2016}} The [[Semiconductor intellectual property core|cores]] in PULPino implement a simple RV32IMC ISA for microcontrollers (Zero-Riscy) or a more powerful RV32IMFC ISA with custom DSP extensions for embedded signal processing. [625] => *[[Western Digital]], in December 2018 announced an RV32IMC core called SweRV EH1 featuring an in-order 2-way superscalar and nine-stage pipeline design. In December 2019, WD announced the SweRV EH2 an in-order core with two hardware threads and a nine-stage pipeline and the SweRV EL2 a single issue core with a 4-stage pipeline{{Cite web|last=Shilov|first=Anton|title=Western Digital Rolls-Out Two New SweRV RISC-V Cores For Microcontrollers|url=https://www.anandtech.com/show/15231/western-digital-rollsout-two-new-swerv-riscv-cores|access-date=2021-02-09|website=www.anandtech.com}} WD plans to use SweRV based processors in their flash controllers and SSDs, and released it as open-source to third parties in January 2019.{{Cite web|last=Shilov|first=Anton|title=Western Digital Reveals SweRV RISC-V Core, Cache Coherency over Ethernet Initiative|url=https://www.anandtech.com/show/13678/western-digital-reveals-swerv-risc-v-core-and-omnixtend-coherency-tech|access-date=2019-05-23|website=www.anandtech.com}}{{Cite web|date=2019-01-28|title=Western Digital Releases SweRV RISC-V Core Source Code|url=https://abopen.com/news/western-digital-releases-swerv-risc-v-core-source-code/|url-status=live|archive-url=https://web.archive.org/web/20190521224239/https://abopen.com/news/western-digital-releases-swerv-risc-v-core-source-code/|archive-date=2019-05-21|website=AB Open|language=en-US}}{{GitHub|chipsalliance/Cores-SweRV}} [626] => * NEORV32 by Stephan Nolting,{{cite journal |last1=Nolting |first1=Stephan|title=neorv32 |url=https://github.com/stnolting/neorv32 |website=GitHub |year=2022 |doi=10.5281/zenodo.7030070 |access-date=9 September 2021}} a highly-configurable 32-bit microcontroller unit (MCU) class RV32[I/E]MACUX_Zbb_Zfinx_Zicsr_Zifencei CPU with on-chip debugger support written in platform-independent [[VHDL]]. The project includes a microcontroller-like SoC that already includes common modules like UART, timers, SPI, TWI, a TRNG and embedded memories. [627] => * [[Alibaba Group]], in July 2019 announced the 2.5 GHz 16-core 64-bit (RV64GCV) XuanTie 910 [[Out-of-order execution#Out-of-order processors|out-of-order]] processor.{{Cite web|url=https://www.techspot.com/news/81177-china-alibaba-making-16-core-25-ghz-risc.html|title=China's Alibaba is making a 16-core, 2.5 GHz RISC-V processor|website=www.techspot.com|date=28 July 2019 |access-date=2019-07-30}} In October 2021 the XuanTie 910 was released as Open-Source.{{cite web |url=https://www.cnx-software.com/2021/10/20/alibaba-open-source-risc-v-cores-xuantie-e902-e906-c906-and-c910/ |title=Alibaba open sources four RISC-V cores: XuanTie E902, E906, C906 and C910 |date=20 October 2021 |access-date=2021-10-20}} [628] => * The Institute of Computing Technology of the [[Chinese Academy of Sciences]] (ICT CAS), in June 2020 launched the XiangShan high-performance RISC-V processor project.[https://github.com/OpenXiangShan/XiangShan XiangShan] repository on Github[https://www.cnx-software.com/2021/07/05/xiangshan-open-source-64-bit-risc-v-processor-rival-arm-cortex-a76/ XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76] - CNX Software [629] => [630] => ==Software== [631] => A normal problem for a new instruction set is a lack of CPU designs and software — both issues limit its usability and reduce adoption. RISC-V has a large number of CPU designs. RISC-V software includes toolchains, operating systems, [[middleware]]{{Vague|reason="Middleware" is a broad term; what sort of middleware requires significant work to handle a new instruction set?|date=July 2022}} and design software. [632] => [633] => Available RISC-V software tools include a [[GNU Compiler Collection]] (GCC) toolchain (with [[GNU Debugger|GDB]], the debugger), an [[LLVM]] toolchain, the [[OVPsim]] simulator (and library of RISC-V Fast Processor Models), the Spike simulator, and a simulator in [[QEMU]] (RV32GC/RV64GC). [https://openjdk.java.net/jeps/422 JEP 422: Linux/RISC-V Port] is already integrated into mainline [[OpenJDK]] repository. Java 21+ Temurin OpenJDK builds for RISC-V are available from [[Adoptium]]. [634] => [635] => Operating system support exists for the [[Linux]] kernel, [[FreeBSD]], [[NetBSD]], and [[OpenBSD]] but the supervisor-mode instructions were unstandardized before version 1.11 of the privileged ISA specification, so this support is provisional. The preliminary FreeBSD port to the RISC-V architecture was upstreamed in February 2016, and shipped in FreeBSD 11.0. Ports of the [[Debian]]{{cite web |url=https://groups.google.com/a/groups.riscv.org/forum/#!msg/sw-dev/u4VcUtB9r94/4HiFYBhXAAAJ |title=Debian GNU/Linux port for RISC-V 64 |last=Montezelo |first=Manuel |website=Google Groups |access-date=19 July 2018}} and [[Fedora (operating system)|Fedora]]{{cite web |url=https://fedoraproject.org/wiki/Architectures/RISC-V |title=Architectures/RISC-V |website=Fedora Wiki |publisher=Red Hat |access-date=26 September 2016}} [[Linux distribution]]s, and a port of [[Haiku (operating system)|Haiku]],{{cite web |title=Booting our RISC-V images |url=https://www.haiku-os.org/blog/kallisti5/2021-11-07_booting_our_risc-v_images/ |website=Haiku Project |access-date=4 March 2023 |language=en |date=7 November 2021}} are stabilizing (all only support 64-bit RISC-V, with no plans to support 32-bit version). A port of [[Das U-Boot]] exists.{{cite web |url=https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/j63wzz2ylY8 |last=Begari |first=Padmarao |title=U-Boot port on RISC-V 32-bit is available |website=Google Groups |publisher=Microsemi |access-date=15 February 2017}} UEFI Spec v2.7 has defined the RISC-V binding and a [[TianoCore]] port has been done by [[Hewlett Packard Enterprise|HPE]] engineers{{GitHub|HewlettPackard/RiscVEdk2}} and is expected to be upstreamed. There is a preliminary port of [[SeL4|the seL4 microkernel]].{{cite web |url=https://docs.sel4.systems/Hardware/RISCV.html |last=Almatary |first=Hesham |title=RISC-V, seL4 |website=seL4 Documentation |publisher=Commonwealth Scientific and Industrial Research Organisation (CSIRO) |access-date=13 July 2018}}{{cite web |url=https://github.com/heshamelmatary |title=heshamelmatary |last=Almatary |first=Hesham |website=GitHub |access-date=13 July 2018}} Hex Five released the first Secure IoT Stack for RISC-V with [[FreeRTOS]] support.{{cite web |url=https://hex-five.com/first-secure-iot-stack-riscv/ | title=MultiZone Secure IoT Stack, the First Secure IoT Stack for RISC-V |website=Hex Five Security |publisher=Hex Five Security, Inc. |access-date=3 Mar 2019| date=22 February 2019 }} Also [[xv6]], a modern reimplementation of [[Version 6 Unix|Sixth Edition Unix]] in [[ANSI C]] used for pedagogical purposes in [[Massachusetts Institute of Technology|MIT]], was ported. Pharos RTOS has been ported to 64-bit RISC-V{{Cite web|url=https://sourceforge.net/projects/rtospharos/|title=Pharos|website=SourceForge|language=en|access-date=1 Apr 2020}} (including time and memory protection). ''Also see'' [[Comparison of real-time operating systems]]. [636] => [637] => A simulator exists to run a RISC-V Linux system on a [[web browser]] using [[JavaScript]].{{cite web|url=https://riscv.org/software-tools/riscv-angel/|title=ANGEL is a Javascript RISC-V ISA (RV64) Simulator that runs riscv-linux with BusyBox.|website=RISCV.org|access-date=17 January 2019|archive-date=11 November 2018|archive-url=https://web.archive.org/web/20181111215351/https://riscv.org/software-tools/riscv-angel/|url-status=dead}}{{Cite web|last=Lee|first=Yunsup|date=2014-03-05|title=Boot RISC-V Linux in your web browser!|url=https://live-risc-v.pantheonsite.io/2014/03/boot-risc-v-linux-in-your-web-browser/|access-date=2020-09-04|website=RISC-V International|language=en-US}}{{Cite web|title=ANGEL – RISC-V|url=http://riscv.org.s3-website-us-west-1.amazonaws.com/angel/index.html|access-date=2020-09-04|website=riscv.org.s3-website-us-west-1.amazonaws.com|archive-url=https://web.archive.org/web/20201201124529/http://riscv.org.s3-website-us-west-1.amazonaws.com/angel/index.html|archive-date=1 December 2020|url-status=dead}} [638] => [639] => [[QEMU]] supports running (using [[binary translation]]) 32- and 64-bit RISC-V systems (e.g. Linux) with many emulated or virtualized devices (serial, parallel, USB, network, storage, real time clock, watchdog, audio), as well as running RISC-V Linux binaries (translating syscalls to the host kernel). It does support multi-core emulation (SMP).{{cite web |title=Documentation/Platforms/RISCV |work=QEMU Wiki |url=https://wiki.qemu.org/Documentation/Platforms/RISCV |access-date=2020-05-07}} [640] => [641] => The Creator simulator is portable and allows the user to learn various assembly languages of different processors (Creator has examples with an implementation of RISC-V and MIPS32 instructions).{{Cite conference|url=https://zenodo.org/record/5130302|title = CREATOR: Simulador didáctico y genérico para la programación en ensamblador|trans-title=CREATOR: Didactic and generic simulator for assembly programming|first1=Diego|last1=Camarmas-Alonso|first2=Felix|last2=Garcia-Carballeira|first3=Elias|last3=Del-Pozo-Puñal|first4=Alejandro Calderon|last4=Mateos|conference=XXXI Jornadas de Paralelismo (JP20/21)|location=Malaga|date = 23 July 2021|language=Spanish|doi=10.5281/zenodo.5130302}}{{Cite conference |title=A new generic simulator for the teaching of assembly programming |url=https://ieeexplore.ieee.org/document/9640144 |date=October 2021 |doi=10.1109/CLEI53233.2021.9640144 |url-access=subscription |publication-date=21 December 2021 |publisher=IEEE |location=Cartago, Costa Rica |lang=es|access-date=August 2, 2022|conference=2021 XLVII Latin American Computing Conference (CLEI) |last1=Camarmas-Alonso |first1=Diego |last2=Garcia-Carballeira |first2=Felix |last3=Del-Pozo-Punal |first3=Elias |last4=Mateos |first4=Alejandro Calderon |pages=1–9 |isbn=978-1-6654-9503-5 |s2cid=245387555 }}CREATOR Web with RISC-V example: https://creatorsim.github.io/creator/?example_set=default_rv&example=e12CREATOR source code on GitHub: https://github.com/creatorsim/creator [642] => [643] => The extensible educational simulator WepSIM implements a ([https://wepsim.github.io/wepsim/ws_dist/?mode=ep&examples_set=Default-RISCV&example=9&simulator=microcode:control_memory¬ify=false microprogrammed]) subset of RISC-V instructions (RV32I+M) and allows the execution of [https://wepsim.github.io/wepsim/ws_dist/wepsim-classic.html?mode=ep&examples_set=Default-RISCV&example=9&simulator=assembly:registers¬ify=false subroutines] in assembly.{{cite web |title=WepSIM with RISC-V_im example |url=https://wepsim.github.io/wepsim/ws_dist/wepsim-classic.html?mode=ep&examples_set=Default-RISCV&example=14&simulator=assembly:registers¬ify=false |work=WepSIM}}{{cite web |title=WepSIM homepage |url=https://wepsim.github.io/}} [644] => [645] => Several languages have been applied to creating RISC-V IP cores including a Scala-based hardware description language, [[Chisel (programming language)|Chisel]],{{cite web|title=Chisel: Constructing Hardware in a Scala Embedded Language|url=https://chisel.eecs.berkeley.edu/|access-date=12 February 2015|website=UC Berkeley|publisher=Regents of the University of California}} which can reduce the designs to [[Verilog]] for use in devices, and the CodAL processor description language which has been used in to describe RISC-V processor cores and to generate corresponding HDKs ([[Register-transfer level|RTL]], testbench and [[Universal Verification Methodology|UVM]]) and SDKs.{{Cite web|title=Codasip Studio|url=https://codasip.com/codasip-studio/|access-date=2021-02-19|website=Codasip|language=en-US}} The RISC-V International Compliance Task Group has a GitHub repository for RV32IMC.{{Citation|title=riscv/riscv-compliance|date=2021-02-12|url=https://github.com/riscv/riscv-compliance|publisher=RISC-V|access-date=2021-02-19}} [646] => [647] => ==Development tools== [648] => * [[IAR Systems]] released the first version of IAR Embedded Workbench for RISC-V, which supports RV32 32-bit RISC-V cores and extensions in the first version. Future releases will include 64-bit support and support for the smaller RV32E base instruction set, as well as functional safety certification and security solutions. [649] => * [[Lauterbach (company)|Lauterbach]] added support for RISC-V to their TRACE32 [[JTAG]] debuggers.{{Cite web|url=https://www.lauterbach.com/frames.html?bdmriscv.html|title=RISC-V Debugger|website=www.lauterbach.com TRACE32 Debugger for RISC-V}}{{Cite web|url=https://www.sifive.com/press/lauterbach-and-sifive-bring-trace32-support-for-high-performance-risc-v-cores|title=Lauterbach and SiFive Bring TRACE32 Support for High-Performance RISC-V Cores|website=www.sifive.com}} Lauterbach also announced{{Cite web|url=https://www.lauterbach.com/frames.html?news_514.html|title=TRACE32 supports SiFive's RISC-V trace|website=www.lauterbach.com|access-date=6 March 2021|archive-date=2 June 2022|archive-url=https://web.archive.org/web/20220602223446/https://www.lauterbach.com/frames.html?news_514.html|url-status=dead}} support for [[SiFive]]s RISC-V [[Nexus (standard)|NEXUS]] based processor trace. [650] => * [[Segger Microcontroller Systems#Debug and trace probes|SEGGER]] released a new product named "J-Trace PRO RISC-V", added support for RISC-V cores to their [[Segger Microcontroller Systems#J-Link|J-Link]] debugging probe family,{{cite web |url=https://www.segger.com/news/segger-adds-support-for-sifives-coreplex-ip-to-its-industry-leading-j-link-debug-probe/ |title=SEGGER Adds Support for SiFive's Coreplex IP to Its Industry Leading J-Link Debug Probe |access-date=2017-09-19}} their integrated development environment Embedded Studio,{{cite web |url=https://www.segger.com/news/segger-embedded-studio-supports-risc-v-architecture/ |title=PR: SEGGER Embedded Studio supports RISC-V architecture |access-date=2017-11-23}} and their RTOS [[embOS]] and embedded software.{{cite web |url=https://www.segger.com/news/segger-presents-rtos-stacks-middleware-for-risc-v/ |title=PR: SEGGER presents RTOS, stacks, middleware for RISC-V |access-date=2017-12-08}} [651] => * [https://www.ultrasoc.com/technology-2/risc-v/ UltraSOC], now part of Siemens,{{Cite web |last=Dahad |first=Nitin |date=2020-06-23 |title=Siemens Acquires UltraSoC for SoC Lifecycle Product Suite |url=https://www.eetimes.com/siemens-acquires-ultrasoc-for-soc-lifecycle-product-suite/ |access-date=2023-07-12 |website=EE Times}} proposed a standard trace system and donated an implementation. [652] => [653] => ==See also== [654] => *[[List of open-source computing hardware]] [655] => *[[Microprocessor chronology]] [656] => [657] => ==Notes== [658] => {{Notelist}} [659] => [660] => ==References== [661] => {{Reflist|30em|refs= [662] => {{cite web [663] => | url = https://riscv.org/contributors/ [664] => | title = Contributors [665] => | website = riscv.org [666] => | publisher = Regents of the University of California [667] => | access-date = 25 August 2014 [668] => | archive-url = https://web.archive.org/web/20180907044920/https://riscv.org/contributors/ [669] => | archive-date = 7 September 2018 [670] => | url-status = dead}} [671] => {{cite web [672] => | last1 = Waterman [673] => | first1 = Andrew [674] => | last2 = Asanović [675] => | first2 = Krste [676] => | author2-link = Krste Asanović [677] => | title = The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.1 [678] => | id = EECS-2016-118 [679] => | url = https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-118.pdf [680] => | date = 31 May 2016 [681] => | publisher = University of California, Berkeley [682] => | access-date = 5 November 2021}} [683] => {{cite web [684] => | last1 = Waterman [685] => | first1 = Andrew [686] => | last2 = Asanović [687] => | first2 = Krste [688] => | author2-link = Krste Asanović [689] => | title = The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.2 | url = https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf [690] => | date = 7 May 2017 [691] => | publisher = RISC-V International [692] => | access-date = 5 November 2021}} [693] => {{cite web [694] => | editor1-last = Waterman [695] => | editor1-first= Andrew [696] => | editor2-last = Asanović [697] => | editor2-first= Krste [698] => | editor2-link = Krste Asanović [699] => | title = The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 20191213 [700] => | url = https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf [701] => | date = December 2019 [702] => | publisher = RISC-V Foundation [703] => | access-date = 5 November 2021}} [704] => {{Cite web [705] => | last1 = Waterman [706] => | first1 = Andrew [707] => | last2 = Asanović [708] => | first2 = Krste [709] => | author2-link = Krste Asanović [710] => | title = The RISC-V Instruction Set Manual Volume II: Privileged Architecture Document Version 20211203 [711] => | url = https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf [712] => | date = 3 December 2021 [713] => | publisher = RISC-V International [714] => | access-date = 5 November 2021}} [715] => {{cite web [716] => | url = https://riscv.org/wp-content/uploads/2015/11/riscv-compressed-spec-v1.9.pdf [717] => | title = The RISC-V Compressed Instruction Set Manual Version 1.9 (draft) [718] => | last = Waterman [719] => | first = Andrew [720] => | display-authors = etal [721] => | website = RISC-V [722] => | access-date = 18 July 2016}} [723] => {{Cite web [724] => | last1 = Newsome [725] => | first1 = Tim [726] => | last2 = Wachs [727] => | first2 = Megan [728] => | title = RISC-V External Debug Support Version 0.13.2 d5029366d59e8563c08b6b9435f82573b603e48e [729] => | url = https://github.com/riscv/riscv-debug-spec/blob/release/riscv-debug-release.pdf [730] => | date = 22 March 2019 [731] => | publisher = RISC-V International [732] => | access-date = 7 November 2021}} [733] => {{cite web [734] => | title = RISC-V History [735] => | url = https://riscv.org/about/history/ [736] => | access-date = 28 January 2023}} [737] => {{cite journal [738] => | last1 = Patterson [739] => | first1 = David A. [740] => | author-link = David Patterson (computer scientist) [741] => | last2 = Ditzel [742] => | first2 = David R. [743] => | title = The Case for the Reduced Instruction Set Computer [744] => | journal = ACM SIGARCH Computer Architecture News [745] => | date = October 1980 [746] => | volume = 8 [747] => | issue = 6 [748] => | page = 25 [749] => | doi = 10.1145/641914.641917| s2cid = 12034303 [750] => }} [751] => {{cite web [752] => | title = Amber ARM-compatible core [753] => | url = http://opencores.org/project,amber [754] => | website = OpenCores [755] => | access-date = 26 August 2014}} [756] => {{cite web [757] => | title = ARM4U [758] => | url = http://opencores.org/project,arm4u [759] => | website = OpenCores [760] => | access-date = 26 August 2014}} [761] => {{cite web [762] => | title = Rocket Core Generator [763] => | url = https://riscv.org/download.html#tab_rocket [764] => | website = RISC-V [765] => | publisher = Regents of the University of California [766] => | access-date = 1 October 2014 [767] => | archive-url = https://web.archive.org/web/20141006085238/https://riscv.org/download.html#tab_rocket [768] => | archive-date= 6 October 2014 [769] => | url-status = dead}} [770] => {{cite book [771] => | last = Waterman [772] => | first = Andrew [773] => | title = Improving Energy Efficiency and Reducing Code Size with RISC-V Compressed [774] => | date = 13 May 2011 [775] => | publisher = Regents of the University of California [776] => | location = U.C. Berkeley [777] => | page = 32 [778] => | url = http://www.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-63.html [779] => | access-date = 25 August 2014}} [780] => {{cite web [781] => | title = SHAKTI Processor Program [782] => | url = https://shakti.org.in [783] => | publisher = Indian Institute of Technology Madras [784] => | access-date = 3 September 2019}} [785] => {{cite web [786] => |title = IIT Madras Open Source Processor Project [787] => |url = http://www.rapidio.org/2014/08/iit-madras-open-source-processor-project/ [788] => |website = Rapid IO [789] => |date = 26 August 2014 [790] => |publisher = IIT Madras [791] => |access-date = 13 September 2014 [792] => |archive-date = 14 September 2014 [793] => |archive-url = https://web.archive.org/web/20140914001234/http://www.rapidio.org/2014/08/iit-madras-open-source-processor-project/ [794] => |url-status = dead [795] => }} [796] => {{cite web [797] => | title = lowRISC website [798] => | url = http://www.lowrisc.org/ [799] => | access-date = 10 May 2015}} [800] => {{cite web [801] => | url = https://freebsdfoundation.blogspot.be/2016/02/initial-freebsd-risc-v-architecture.html [802] => | title = FreeBSD Foundation: Initial FreeBSD RISC-V Architecture Port Committed [803] => | date = 4 February 2016}} [804] => {{cite web [805] => | url = https://wiki.freebsd.org/riscv [806] => | title = riscv - FreeBSD Wiki [807] => | website = wiki.freebsd.org}} [808] => }} [809] => [810] => ==Further reading== [811] => {{Library resources box}} [812] => * {{cite web|url=https://riscv.org/technical/specifications/|title=The RISC-V Instruction Set Manual |publisher=RISC-V International}} [813] => {{refbegin}} [814] => * {{cite web [815] => | url = https://github.com/johnwinans/rvalp [816] => | title = RISC-V Assembly Language Programming [817] => | website = GitHub [818] => | date = 8 November 2019}} [819] => * {{cite web [820] => | last1 = Waterman [821] => | first1 = Andrew [822] => | url = https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-1.pdf [823] => | title = Design of the RISC-V Instruction Set Architecture [824] => | date = January 2016 [825] => | id = EECS-2016-1 [826] => | website = EECS Department, University of California, Berkeley}} [827] => * {{cite web [828] => | url = https://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.html [829] => | title = Instruction Sets Should Be Free: The Case For RISC-V [830] => | last1 = Asanović [831] => | first1 = Krste [832] => | author1-link = Krste Asanović [833] => | last2 = Patterson [834] => | first2 = David A. [835] => | author2-link = David Patterson (computer scientist) [836] => | date = 6 August 2014 [837] => | id = UCB/EECS-2014-146 [838] => | website = EECS Department, University of California, Berkeley}} [839] => * {{cite conference [840] => | url = https://www.hotchips.org/wp-content/uploads/hc_archives/hc25/HC25-posters/HC25.26.p70-RISC-V-Warterman-UCB.pdf [841] => | title = The RISC-V Instruction Set [842] => | last1 = Waterman [843] => | first1 = Andrew [844] => | last2 = Lee [845] => | first2 = Yunsup [846] => | last3 = Avizienis [847] => | first3 = Rimas [848] => | last4 = Cook [849] => | first4 = Henry [850] => | last5 = Patterson [851] => | first5 = David A. [852] => | author5-link = David Patterson (computer scientist) [853] => | last6 = Asanović [854] => | first6 = Krste [855] => | author6-link = Krste Asanović [856] => | date = 25–27 August 2013 [857] => | conference = Hot Chips 25 [858] => | conference-url = https://www.hotchips.org/archives/2010s/hc25/ [859] => | location = Stanford University, Palo Alto, California, USA [860] => }} [861] => * {{cite conference [862] => | url = https://riscv.org/wp-content/uploads/2015/02/riscv-software-toolchain-tutorial-hpca2015.pdf [863] => | title = RISC-V Software Ecosystem [864] => | last = Dabbelt [865] => | first = Palmer [866] => | date = 7–11 February 2015 [867] => | conference = High-Performance Computer Architecture (HPCA) 2015 [868] => | conference-url = http://darksilicon.org/hpca/ [869] => | location = San Francisco, California, USA [870] => }} [871] => * {{cite conference [872] => | url = https://riscv.org/wp-content/uploads/2015/02/riscv-rocket-chip-generator-tutorial-hpca2015.pdf [873] => | title = RISC-V "Rocket Chip" SoC Generator in Chisel [874] => | last = Lee [875] => | first = Yunsup [876] => | date = 7–11 February 2015 [877] => | conference = High-Performance Computer Architecture (HPCA) 2015 [878] => | conference-url = http://darksilicon.org/hpca/ [879] => | location = San Francisco, California, USA [880] => }} [881] => * {{cite web [882] => | url = https://riscv.org/wp-content/uploads/2015/11/riscv-compressed-spec-v1.9.pdf [883] => | title = The RISC-V Compressed Instruction Set Manual Version 1.9 (draft) [884] => | last1 = Waterman [885] => | first1 = Andrew [886] => | last2 = Lee [887] => | first2 = Yunsup [888] => | last3 = Patterson [889] => | first3 = David A. [890] => | author3-link = David Patterson (computer scientist) [891] => | last4 = Asanović [892] => | first4 = Krste [893] => | author4-link = Krste Asanović [894] => | date = 5 November 2015 [895] => | website = RISC-V}} [896] => {{refend}} [897] => [898] => ==External links== [899] => {{Commons category}} [900] => * {{Official website}} [901] => * {{GitHub|jameslzhu/riscv-card|RISC-V Instruction Set Reference Card}} [902] => * {{cite web [903] => | url = https://www.eetimes.com/risc-v-an-open-standard-for-socs/ [904] => | title = RISC-V: An Open Standard for SoCs [905] => | date = 8 July 2014 [906] => | website = EETimes}} [907] => * {{cite web [908] => | url = http://www.adapteva.com/andreas-blog/analyzing-the-risc-v-instruction-set-architecture/ [909] => | title = Analyzing the RISC-V Instruction Set Architecture [910] => | date = 11 August 2014 [911] => | website = [[Adapteva]]}} [912] => *{{cite tech report |last1=Celio |first1=Christopher |last2=Dabbelt |first2=Palmer |last3=Patterson |first3=David A. |author3-link=David Patterson (computer scientist) |last4=Asanović |first4=Krste |author4-link=Krste Asanović |title=The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V |date=8 July 2016 |publisher=University of California, Berkeley |arxiv=1607.02318 |id=UCB/EECS-2016-130}} [913] => * {{cite web [914] => | url = https://www.electromaker.io/blog/article/what-is-risc-v [915] => | title = What is RISC-V? [916] => | date = 14 July 2021 [917] => | website = Electromaker}} [918] => [919] => {{RISC architectures}} [920] => {{Programmable logic}} [921] => {{Microcontrollers}} [922] => [923] => [[Category:64-bit computers]] [924] => [[Category:Computer-related introductions in 2010]] [925] => [[Category:Instruction set architectures]] [926] => [[Category:Microcontrollers]] [927] => [[Category:Open microprocessors]] [928] => [[Category:Lists of microprocessors]] [] => )
good wiki

RISC-V

RISC-V is an open-source instruction set architecture (ISA) that is designed to be simple, modular, and extensible. It was developed at the University of California, Berkeley and has gained significant attention and adoption in both industry and academia.

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About

It was developed at the University of California, Berkeley and has gained significant attention and adoption in both industry and academia. The RISC-V ISA allows for different implementations and customization, making it suitable for a wide range of applications, from embedded systems and smartphones to supercomputers. Its modular design enables users to select the set of instructions that best suits their needs, which promotes flexibility and efficiency. One of the key advantages of RISC-V is its open-source nature, allowing anyone to use, modify, and contribute to the ISA. This has led to a thriving community of developers and companies actively supporting and advancing the architecture. In addition to the base instruction set, RISC-V also includes several optional extensions, such as floating-point operations, atomic instructions, and vector operations, among others, which can be added depending on the particular requirements of the application. The RISC-V Foundation, a non-profit organization, oversees the development and promotion of the RISC-V ISA. It coordinates technical activity, educates the community, and fosters collaboration among industry and academic partners. The foundation also maintains the official specifications and provides certification programs for RISC-V implementations. The Wikipedia page on RISC-V provides a comprehensive overview of the ISA, its history, design principles, instruction formats, and extensions. It also covers notable implementations, companies using RISC-V, and the various software tools and ecosystems available for development with RISC-V. Overall, the page serves as a valuable resource for those looking to understand the RISC-V ISA and its growing impact on the computer architecture industry.

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