Array ( [0] => {{Use dmy dates|date=May 2022}} [1] => {{Short description|64-bit extension of the ARM architecture}} [2] => {{Too technical|date=June 2020}} [3] => [4] => [[File:ARMCortexA57A53.jpg|thumb|Armv8-A platform with [[ARM Cortex-A57|Cortex-A57]]/[[ARM Cortex-A53|A53]] MPCore [[ARM big.LITTLE|big.LITTLE]] CPU chip]] [5] => '''AArch64''' or '''ARM64''' is the [[64-bit]] extension of the [[ARM architecture family]]. It was first introduced with the [[Armv8-A]] architecture, and had many extension updates.{{Cite web | url=https://developer.arm.com/documentation/102378/0201 | title=Overview | work=Learn the architecture: Understanding the Armv8.x and Armv9.x extensions}} [6] => [7] => =={{anchor|ARM8-A}}ARM-A (application architecture) == [8] => {{See also|Comparison of ARMv8-A processors}} [9] => Announced in October 2011,{{cite press release|url=https://www.arm.com/about/newsroom/arm-discloses-technical-details-of-the-next-version-of-the-arm-architecture.php|title=ARM Discloses Technical Details Of The Next Version Of The ARM Architecture|date=27 October 2011|publisher=[[Arm Holdings]]|access-date=20 September 2013|archive-url=https://web.archive.org/web/20190101024118/https://www.arm.com/about/newsroom/arm-discloses-technical-details-of-the-next-version-of-the-arm-architecture.php|archive-date=1 January 2019}} '''ARMv8-A''' represents a fundamental change to the ARM architecture. It adds an optional 64-bit architecture, named "AArch64", and the associated new "A64" instruction set. AArch64 provides [[user space|user-space]] compatibility with the existing 32-bit architecture ("AArch32" / ARMv7-A), and instruction set ("A32"). The 16-32bit Thumb instruction set is referred to as "T32" and has no 64-bit counterpart. ARMv8-A allows 32-bit applications to be executed in a 64-bit OS, and a 32-bit OS to be under the control of a 64-bit [[hypervisor]].{{cite web | url=https://www.arm.com/files/downloads/ARMv8_Architecture.pdf | title=ARMv8-A Technology Preview | year=2011 | access-date=31 October 2011 | first=Richard | last=Grisenthwaite | archive-date=11 November 2011 | archive-url=https://web.archive.org/web/20111111161327/https://www.arm.com/files/downloads/ARMv8_Architecture.pdf | url-status=dead }} ARM announced their [[ARM Cortex-A53|Cortex-A53]] and [[ARM Cortex-A57|Cortex-A57]] cores on 30 October 2012.{{cite press release | url=https://www.arm.com/about/newsroom/arm-launches-cortex-a50-series-the-worlds-most-energy-efficient-64-bit-processors.php | title=ARM Launches Cortex-A50 Series, the World's Most Energy-Efficient 64-bit Processors | publisher=[[Arm Holdings]] | access-date=31 October 2012}} [[Apple Inc.|Apple]] was the first to release an ARMv8-A compatible core ([[Apple A7|Cyclone]]) in a consumer product ([[iPhone 5S]]). [[AppliedMicro]], using an [[Field-programmable gate array|FPGA]], was the first to demo ARMv8-A.{{cite press release |url=https://www.businesswire.com/news/home/20111027006673/en/AppliedMicro-Showcases-World's-64-bit-ARM-v8-Core |title=AppliedMicro Showcases World's First 64-bit ARM v8 Core |publisher=AppliedMicro |date=28 October 2011 |access-date=11 February 2014}} The first ARMv8-A [[System on a chip|SoC]] from [[Samsung Electronics|Samsung]] is the Exynos 5433 used in the [[Samsung Galaxy Note 4|Galaxy Note 4]], which features two clusters of four Cortex-A57 and Cortex-A53 cores in a [[ARM big.LITTLE|big.LITTLE]] configuration; but it will run only in AArch32 mode.{{cite web | title = Samsung's Exynos 5433 is an A57/A53 ARM SoC |publisher = AnandTech |url = https://www.anandtech.com/show/8537/samsungs-exynos-5433-is-an-a57a53-arm-soc | access-date = 17 September 2014}} [10] => [11] => ARMv8-A includes the VFPv3/v4 and advanced SIMD (Neon) as standard features in both AArch32 and AArch64. It also adds cryptography instructions supporting [[Advanced Encryption Standard|AES]], [[SHA-1]]/[[SHA-256]] and [[finite field arithmetic]].{{cite web|title=ARM Cortex-A53 MPCore Processor Technical Reference Manual: Cryptography Extension|url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0500e/CJHDEBAF.html|publisher=ARM|access-date=11 September 2016}} [12] => [13] => === Naming conventions === [14] => * 64 + 32 bit: [15] => ** Architecture: AArch64. [16] => ** Specification: ARMv8-A. [17] => ** Instruction sets: A64 + A32. [18] => ** Suffixes: v8-A [19] => * 32 + 16 (Thumb) bit: [20] => ** Architecture: AArch32. [21] => ** Specification: ARMv8-R / ARMv7-A. [22] => ** Instruction sets: A32 + T32. [23] => ** Suffixes: -A32 / -R / v7-A. [24] => ** Example: ARMv8-R, Cortex-A32.{{cite web|url=https://www.arm.com/products/processors/cortex-a/cortex-a32-processor.php|title=Cortex-A32 Processor – ARM|access-date=18 December 2016}} [25] => [26] => === AArch64 features === [27] => * New instruction set, A64: [28] => ** Has 31 general-purpose 64-bit registers. [29] => ** Has dedicated zero or stack pointer (SP) register (depending on instruction). [30] => ** The program counter (PC) is no longer directly accessible as a register. [31] => ** Instructions are still 32 bits long and mostly the same as A32 (with LDM/STM instructions and most conditional execution dropped). [32] => *** Has paired loads/stores (in place of LDM/STM). [33] => *** No [[Branch predication|predication]] for most instructions (except branches). [34] => ** Most instructions can take 32-bit or 64-bit arguments. [35] => ** Addresses assumed to be 64-bit. [36] => * Advanced [[Single instruction, multiple data|SIMD]]{{anchor|SIMD}} (Neon) enhanced: [37] => ** Has 32 × 128-bit registers (up from 16), also accessible via VFPv4. [38] => ** Supports [[double-precision floating-point format]]. [39] => ** Fully [[IEEE 754]] compliant. [40] => ** AES encrypt/decrypt and SHA-1/SHA-2 hashing instructions also use these registers. [41] => * A new exception system: [42] => ** Fewer banked registers and modes. [43] => * Memory translation from 48-bit virtual addresses based on the existing Large Physical Address Extension (LPAE), which was designed to be easily extended to 64-bit. [44] => [45] => Extension: Data gathering hint (ARMv8.0-DGH). [46] => [47] => AArch64 was introduced in ARMv8-A and is included in subsequent versions of ARMv8-A. It was also introduced in ARMv8-R as an option, after its introduction in ARMv8-A; it is not included in ARMv8-M. [48] => [49] => ==== Instruction formats ==== [50] => The main opcode for selecting which group an A64 instruction belongs to is at bits 25-28. [51] => {| class="wikitable mw-collapsible mw-collapsed" style="text-align:center;" [52] => |+ A64 instruction formats [53] => |- [54] => ! rowspan=2 | Type [55] => ! colspan=32 | Bit [56] => |- [57] => ! 31 !! 30 !! 29 !! 28 !! 27 !! 26 !! 25 !! 24 !! 23 !! 22 !! 21 !! 20 !! 19 !! 18 !! 17 !! 16 !! 15 !! 14 !! 13 !! 12 !! 11 !! 10 !! 9 !! 8 !! 7 !! 6 !! 5 !! 4 !! 3 !! 2 !! 1 !! 0 [58] => |- [59] => | Reserved [60] => | 0 [61] => | colspan="2" | op{{sub|0}} [62] => | 0 || 0 || 0 || 0 [63] => | colspan="9" | op{{sub|1}} [64] => | colspan="16" | [65] => |- [66] => | {{abbr|SME|Scalable Matrix Extensions}} [67] => | 1 [68] => | colspan="2" | op{{sub|0}} [69] => | 0 || 0 || 0 || 0 [70] => | colspan="25" | Varies [71] => |- [72] => | Unallocated [73] => | colspan="3" | [74] => | 0 || 0 || 0 || 1 [75] => | colspan="25" | [76] => |- [77] => | {{abbr|SVE|Scalable Vector Extensions}} [78] => | colspan="3" | [79] => | 0 || 0 || 1 || 0 [80] => | colspan="25" | Varies [81] => |- [82] => | Unallocated [83] => | colspan="3" | [84] => | 0 || 0 || 1 || 1 [85] => | colspan="25" | [86] => |- [87] => | Data Processing — Immediate PC-rel. [88] => |op ||colspan="2"|imm{{sub|lo}} ||1 ||0 ||0 ||0 ||0 ||colspan="19"|imm{{sub|hi}} ||colspan="5|Rd [89] => |- [90] => | Data Processing — Immediate Others [91] => |sf ||colspan="2"| ||1 || 0 || 0 ||colspan="2"|01-11 ||colspan="19"| ||colspan="5|Rd [92] => |- [93] => | Branches + System Instructions [94] => |colspan="3"|op0 ||1 ||0 ||1 || colspan="14"|op1 ||colspan="7"| ||colspan="5|op2 [95] => |- [96] => | Load and Store Instructions [97] => |colspan="4"|op0 ||1 ||op1 ||0 ||colspan="2"|op2 || ||colspan="6"|op3 ||colspan="4"| ||colspan="2"|op4 ||colspan="10"| [98] => |- [99] => | Data Processing — Register [100] => |sf ||op0|| ||op1 ||1 ||0 ||1 ||colspan="4"|op2 ||colspan="5"| ||colspan="6"|op3 ||colspan="10"| [101] => |- [102] => | Data Processing — Floating Point and SIMD [103] => |colspan="4"|op0||1||1||1||colspan="2"|op1||colspan="4"|op2||colspan="9"|op3||colspan="10"| [104] => |} [105] => [106] => === ARMv8.1-A === [107] => In December 2014, ARMv8.1-A,{{cite web |url=https://community.arm.com/groups/processors/blog/2014/12/02/the-armv8-a-architecture-and-its-ongoing-development |title=The ARMv8-A architecture and its ongoing development |first=David |last=Brash |date=2 December 2014 |access-date=23 January 2015}} an update with "incremental benefits over v8.0", was announced. The enhancements fell into two categories: changes to the instruction set, and changes to the exception model and memory translation. [108] => [109] => Instruction set enhancements included the following: [110] => [111] => * A set of AArch64 atomic read-write instructions. [112] => * Additions to the Advanced SIMD instruction set for both AArch32 and AArch64 to enable opportunities for some library optimizations: [113] => ** Signed Saturating Rounding Doubling Multiply Accumulate, Returning High Half. [114] => ** Signed Saturating Rounding Doubling Multiply Subtract, Returning High Half. [115] => ** The instructions are added in vector and scalar forms. [116] => * A set of AArch64 load and store instructions that can provide memory access order that is limited to configurable address regions. [117] => * The optional CRC instructions in v8.0 become a requirement in ARMv8.1. [118] => [119] => Enhancements for the exception model and memory translation system included the following: [120] => [121] => * A new Privileged Access Never (PAN) state bit provides control that prevents privileged access to user data unless explicitly enabled. [122] => * An increased VMID range for virtualization; supports a larger number of virtual machines. [123] => * Optional support for hardware update of the page table access flag, and the standardization of an optional, hardware updated, dirty bit mechanism. [124] => * The Virtualization Host Extensions (VHE). These enhancements improve the performance of Type 2 hypervisors by reducing the software overhead associated when transitioning between the Host and Guest operating systems. The extensions allow the Host OS to execute at EL2, as opposed to EL1, without substantial modification. [125] => * A mechanism to free up some translation table bits for operating system use, where the hardware support is not needed by the OS. [126] => * [[Top byte ignore]] for [[memory tagging]].{{Cite web|url=https://en.wikichip.org/wiki/arm/tbi|title=Top-byte ignore (TBI)|website=WikiChip}} [127] => [128] => === ARMv8.2-A === [129] => In January 2016, ARMv8.2-A was announced.{{cite web|url=https://community.arm.com/groups/processors/blog/2016/01/05/armv8-a-architecture-evolution|title=ARMv8-A architecture evolution|first=David|last=Brash|date=5 January 2016|access-date=7 June 2016}} Its enhancements fell into four categories: [130] => [131] => * Optional [[Half-precision floating-point format|half-precision floating-point]] data processing (half-precision was already supported, but not for processing, just as a storage format.) [132] => * Memory model enhancements. [133] => * Introduction of [[reliability, availability and serviceability|Reliability, Availability and Serviceability Extension]] (RAS Extension). [134] => * Introduction of statistical profiling. [135] => [136] => {{anchor|ARMv8-A SVE}} [137] => ==== Scalable Vector Extension (SVE) {{anchor|Scalable vector extension}} ==== [138] => The Scalable Vector Extension (SVE) is "an optional extension to the ARMv8.2-A architecture and newer" developed specifically for vectorization of [[high-performance computing]] scientific workloads.{{Cite news|url=https://community.arm.com/processors/b/blog/posts/technology-update-the-scalable-vector-extension-sve-for-the-armv8-a-architecture|title=The scalable vector extension sve for the ARMv8 a architecture|work=Arm Community|access-date=8 July 2018|language=en|date=22 August 2016}}{{Cite web|url=https://gcc.gnu.org/gcc-8/changes.html|title=GCC 8 Release Series – Changes, New Features, and Fixes – GNU Project – Free Software Foundation (FSF)|website=gcc.gnu.org|language=en|access-date=9 July 2018}} The specification allows for variable vector lengths to be implemented from 128 to 2048 bits. The extension is complementary to, and does not replace, the [[ARM architecture#Advanced SIMD (Neon)|NEON]] extensions. [139] => [140] => A 512-bit SVE variant has already been implemented on the [[Fugaku (supercomputer)|Fugaku supercomputer]] using the [[Fujitsu A64FX]] ARM processor; this computer{{Cite press release|url=https://www.fujitsu.com/global/about/resources/news/press-releases/2018/0621-01.html|title=Fujitsu Completes Post-K Supercomputer CPU Prototype, Begins Functionality Trials – Fujitsu Global|website=www.fujitsu.com|language=en|access-date=8 July 2018}} was the fastest supercomputer in the world for two years, from June 2020{{Cite press release|title=Japan's Fugaku gains title as world's fastest supercomputer|url=https://www.riken.jp/en/news_pubs/news/2020/20200623_1/index.html |date=23 June 2020 |access-date=7 December 2020 |publisher=www.riken.jp |language=en}} to May 2022.{{cite web |title=ORNL's Frontier First to Break the Exaflop Ceiling |url=https://www.top500.org/news/ornls-frontier-first-to-break-the-exaflop-ceiling/ |website=[[Top500]] |date=30 May 2022 |access-date=30 May 2022 }} A more flexible version, 2x256 SVE, was implemented by the [[AWS Graviton|AWS Graviton3]] ARM processor. [141] => [142] => SVE is supported by the [[GNU Compiler Collection|GCC]] compiler, with GCC 8 supporting automatic vectorization and GCC 10 supporting C intrinsics. {{as of|July 2020}}, [[LLVM]] and [[clang]] support C and IR intrinsics. ARM's own fork of LLVM supports auto-vectorization.{{cite web |title=⚙ D71712 Downstream SVE/SVE2 implementation (LLVM) |url=https://reviews.llvm.org/D71712 |website=reviews.llvm.org}} [146] => [147] => === ARMv8.3-A === [148] => In October 2016, ARMv8.3-A was announced. Its enhancements fell into six categories:{{cite web|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv8-a-architecture-2016-additions|title=ARMv8-A architecture – 2016 additions|author=David Brash|date=26 October 2016}} [149] => [150] => * Pointer authentication.{{cite web |url=https://patches.linaro.org/patch/90145/ |title=[Ping~,AArch64] Add commandline support for -march=armv8.3-a |quote=pointer authentication extension is defined to be mandatory extension on ARMv8.3-A and is not optional}} (AArch64 only); mandatory extension (based on a new block cipher, [[QARMA]]{{cite web|url=https://www.qualcomm.com/news/onq/2017/01/10/qualcomm-releases-whitepaper-detailing-pointer-authentication-armv83|title=Qualcomm releases whitepaper detailing pointer authentication on ARMv8.3|date=10 January 2017}}) to the architecture (compilers need to exploit the security feature, but as the instructions are in NOP space, they are backwards compatible albeit providing no extra security on older chips). [151] => * Nested virtualization (AArch64 only). [152] => * Advanced SIMD [[complex number]] support (AArch64 and AArch32); e.g. rotations by multiples of 90 degrees. [153] => * New FJCVTZS (Floating-point [[JavaScript]] Convert to Signed fixed-point, rounding toward Zero) instruction.{{cite web|url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100069_0610_00_en/hko1477562192868.html |title=A64 Floating-point Instructions: FJCVTZS |website=arm.com |access-date=11 July 2019}} [154] => * A change to the memory consistency model (AArch64 only); to support the (non-default) weaker RCpc (Release Consistent processor consistent) model of [[C++11]]/[[C11 (C standard revision)|C11]] (the default C++11/C11 consistency model was already supported in previous ARMv8). [155] => * ID mechanism support for larger system-visible caches (AArch64 and AArch32). [156] => [157] => ARMv8.3-A architecture is now supported by (at least) the [[GNU Compiler Collection|GCC]] 7 compiler.{{cite web|url=https://gcc.gnu.org/gcc-7/changes.html |title=GCC 7 Release Series – Changes, New Features, and Fixes |quote=The ARMv8.3-A architecture is now supported. It can be used by specifying the -march=armv8.3-a option. [..] The option -msign-return-address= is supported to enable return address protection using ARMv8.3-A Pointer Authentication Extensions.}} [162] => [163] => === ARMv8.4-A === [164] => In November 2017, ARMv8.4-A was announced. Its enhancements fell into these categories:{{Cite web|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/introducing-2017s-extensions-to-the-arm-architecture|title=Introducing 2017's extensions to the Arm Architecture|website=community.arm.com|date=2 November 2017 |language=en|access-date=15 June 2019}}{{Cite web|url=https://community.arm.com/developer/tools-software/tools/b/tools-software-ides-blog/posts/exploring-the-arm-dot-product-instructions|title=Exploring dot product machine learning|website=community.arm.com|date=6 December 2017 |language=en|access-date=15 June 2019}}{{Cite web|url=https://www.phoronix.com/scan.php?page=news_item&px=GCC-ARMv8.4-A-Patches|title=ARM Preps ARMv8.4-A Support For GCC Compiler – Phoronix|website=www.phoronix.com|language=en|access-date=14 January 2018}} [165] => [166] => * "SHA3 / SHA512 / SM3 / [[SM4 algorithm|SM4]] crypto extensions." [167] => * Improved virtualization support. [168] => * Memory Partitioning and Monitoring (MPAM) capabilities. [169] => * A new Secure EL2 state and Activity Monitors. [170] => * Signed and unsigned integer [[dot product]] (SDOT and UDOT) instructions. [171] => [172] => === ARMv8.5-A and ARMv9.0-A === [173] => {{anchor|ARMv8.5-A|ARMv9.0-A}} [174] => In September 2018, ARMv8.5-A was announced. Its enhancements fell into these categories:{{Cite web | url=https://developer.arm.com/documentation/102378/0201/ARMv8-x-and-ARMv9-x-extensions-and-features | title=ARMv8.x and ARMv9.x extensions and features | work=Learn the architecture: Understanding the ARMv8.x and ARMv9.x extensions}}{{Cite web|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-a-profile-architecture-2018-developments-armv85a|title=Arm Architecture ARMv8.5-A Announcement – Processors blog – Processors – Arm Community|website=community.arm.com|language=en|access-date=26 April 2019}}{{Cite web|url=https://developer.arm.com/docs/ddi0487/ea|title=Arm Architecture Reference Manual ARMv8, for ARMv8-A architecture profile|website=ARM Developer|language=en|access-date=6 August 2019}} [175] => * Memory Tagging Extension (MTE) (AArch64).{{Cite web|title=Arm MTE architecture: Enhancing memory safety|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/enhancing-memory-safety|access-date=27 July 2021|website=community.arm.com|date=5 August 2019 |language=en}} [176] => * Branch Target Indicators (BTI) (AArch64) to reduce "the ability of an attacker to execute arbitrary code". Like pointer authentication, the relevant instructions are no-ops on earlier versions of ARMv8-A. [177] => * Random Number Generator instructions – "providing Deterministic and True Random Numbers conforming to various National and International Standards". [178] => [179] => On 2 August 2019, [[Google]] announced [[Android (operating system)|Android]] would adopt Memory Tagging Extension (MTE).{{Cite web|url=https://security.googleblog.com/2019/08/adopting-arm-memory-tagging-extension.html|title=Adopting the Arm Memory Tagging Extension in Android|website=Google Online Security Blog|language=en|access-date=6 August 2019}} [180] => [181] => [183] => [184] => {{anchor|ARMv9-A}} [185] => In March 2021, ARMv9-A was announced. ARMv9-A's baseline is all the features from ARMv8.5.{{Cite web|title=Arm's solution to the future needs of AI, security and specialized computing is v9|url=https://www.arm.com/company/news/2021/03/arms-answer-to-the-future-of-ai-armv9-architecture|access-date=27 July 2021|website=Arm {{!}} The Architecture for the Digital World|language=en}}{{Cite web|last=Schor|first=David|date=30 March 2021|title=Arm Launches ARMv9|url=https://fuse.wikichip.org/news/4646/arm-launches-armv9/|access-date=27 July 2021|website=WikiChip Fuse|language=en-US}}{{Cite web|last=Frumusanu|first=Andrei|title=Arm Announces ARMv9 Architecture: SVE2, Security, and the Next Decade|url=https://www.anandtech.com/show/16584/arm-announces-armv9-architecture|access-date=27 July 2021|website=www.anandtech.com}} ARMv9-A also adds: [186] => [187] => * Scalable Vector Extension 2 (SVE2). SVE2 builds on SVE's scalable vectorization for increased fine-grain [[Data-level parallelism|Data Level Parallelism (DLP)]], to allow more work done per instruction. SVE2 aims to bring these benefits to a wider range of software including DSP and multimedia SIMD code that currently use [[#SIMD|Neon]]. The [[LLVM]]/[[Clang]] 9.0 and [[GNU Compiler Collection|GCC]] 10.0 development codes were updated to support SVE2.{{Cite web|title=Arm SVE2 Support Aligning For GCC 10, LLVM Clang 9.0 – Phoronix|url=https://www.phoronix.com/scan.php?page=news_item&px=Arm-SVE2-GCC10-Clang9|access-date=26 May 2019|website=www.phoronix.com}} [188] => * Transactional Memory Extension (TME). Following [[Transactional Synchronization Extensions|the x86 extensions]], TME brings support for [[Transactional memory|Hardware Transactional Memory (HTM)]] and Transactional Lock Elision (TLE). TME aims to bring scalable concurrency to increase coarse-grained [[Thread-level parallelism|Thread Level Parallelism (TLP)]], to allow more work done per thread.{{Cite web|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/new-technologies-for-the-arm-a-profile-architecture|title=Arm releases SVE2 and TME for A-profile architecture – Processors blog – Processors – Arm Community|website=community.arm.com|date=18 April 2019 |language=en|access-date=25 May 2019}} The [[LLVM]]/[[Clang]] 9.0 and [[GNU Compiler Collection|GCC]] 10.0 development codes were updated to support TME. [189] => * Confidential Compute Architecture (CCA).{{Cite web|title=Unlocking the power of data with Arm CCA|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/unlocking-the-power-of-data-with-arm-cca|access-date=27 July 2021|website=community.arm.com|date=23 June 2021 |language=en}}{{Cite web|date=23 June 2021|title=Arm Introduces Its Confidential Compute Architecture|url=https://fuse.wikichip.org/news/5699/arm-introduces-its-confidential-compute-architecture/|access-date=27 July 2021|website=WikiChip Fuse|language=en-US}} [190] => [191] => === ARMv8.6-A and ARMv9.1-A === [192] => {{anchor|ARMv8.6-A|ARMv9.1-A}} [193] => In September 2019, ARMv8.6-A was announced. Its enhancements fell into these categories:{{Cite web|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a|title=Arm A profile architecture update 2019|website=community.arm.com|date=25 September 2019 |language=en|access-date=26 September 2019}} [194] => * General Matrix Multiply (GEMM). [195] => * [[bfloat16 floating-point format|Bfloat16 format]] support. [196] => * SIMD matrix manipulation instructions, BFDOT, BFMMLA, BFMLAL and BFCVT. [197] => * Enhancements for virtualization, system management and security. [198] => * And the following extensions (that [[LLVM]] 11 already added support for{{Cite web|url=https://releases.llvm.org/11.0.1/docs/ReleaseNotes.html|title=LLVM 11.0.0 Release Notes|access-date=11 March 2021|website=releases.llvm.org}}): [199] => ** Enhanced Counter Virtualization (ARMv8.6-ECV). [200] => ** Fine-Grained Traps (ARMv8.6-FGT). [201] => ** Activity Monitors virtualization (ARMv8.6-AMU). [202] => [203] => For example, fine-grained traps, Wait-for-Event (WFE) instructions, EnhancedPAC2 and FPAC. The bfloat16 extensions for SVE and Neon are mainly for deep learning use.{{Cite web|url=https://community.arm.com/developer/ip-products/processors/b/ml-ip-blog/posts/bfloat16-processing-for-neural-networks-on-armv8_2d00_a|title=BFloat16 extensions for ARMv8-A|website=community.arm.com|date=29 August 2019 |language=en|access-date=30 August 2019}} [204] => [205] => === ARMv8.7-A and ARMv9.2-A === [206] => {{anchor|ARMv8.7-A|ARMv9.2-A}} [207] => In September 2020, ARMv8.7-A was announced. Its enhancements fell into these categories:{{cite web |last1=Weidmann |first1=Martin |title=Arm A-Profile Architecture Developments 2020 |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2020 |website=community.arm.com |publisher=ARM |access-date=28 September 2022 |date=21 September 2020}} [208] => * Scalable Matrix Extension (SME)(ARMv9.2 only).{{Cite web|title=Scalable Matrix Extension for the ARMv9-A Architecture|url=https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/scalable-matrix-extension-armv9-a-architecture|access-date=27 July 2021|website=community.arm.com|date=14 July 2021 |language=en}} SME adds new features to process matrices efficiently, such as: [209] => ** Matrix tile storage. [210] => ** On-the-fly matrix transposition. [211] => ** Load/store/insert/extract tile vectors. [212] => ** Matrix outer product of SVE vectors. [213] => ** "Streaming mode" SVE. [214] => * Enhanced support for PCIe hot plug (AArch64). [215] => * Atomic 64-byte load and stores to accelerators (AArch64). [216] => * Wait For Instruction (WFI) and Wait For Event (WFE) with timeout (AArch64). [217] => * Branch-Record recording (ARMv9.2 only). [218] => [219] => === ARMv8.8-A and ARMv9.3-A === [220] => {{anchor|ARMv8.8-A|ARMv9.3-A}} [221] => In September 2021, ARMv8.8-A and ARMv9.3-A were announced. Their enhancements fell into these categories:{{cite web |last1=Weidmann |first1=Martin |title=Arm A-Profile Architecture Developments 2021 |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2021 |website=community.arm.com |publisher=ARM |access-date=28 September 2022 |date=8 September 2021}} [222] => * Non-maskable interrupts (AArch64). [223] => * Instructions to optimize memcpy() and memset() style operations (AArch64). [224] => * Enhancements to PAC (AArch64). [225] => * Hinted conditional branches (AArch64). [226] => [227] => [[LLVM]] 15 supports ARMv8.8-A and ARMv9.3-A.{{cite web |title=What is New in LLVM 15? - Architectures and Processors blog - Arm Community blogs - Arm Community |date=27 February 2023 |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/llvm-15 |access-date=2023-04-15}} [228] => [229] => === ARMv8.9-A and ARMv9.4-A === [230] => {{anchor|ARMv8.9-A|ARMv9.4-A}} [231] => In September 2022, ARMv8.9-A and ARMv9.4-A were announced, including:{{Cite web |title=Arm A-Profile Architecture Developments 2022 - Architectures and Processors blog - Arm Community blogs - Arm Community |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022 |access-date=2022-12-09 |website=community.arm.com |date=29 September 2022 |language=en}} [232] => [233] => * Virtual Memory System Architecture (VMSA) enhancements. [234] => ** Permission indirection and overlays. [235] => ** Translation hardening. [236] => ** 128-bit translation tables (ARMv9 only). [237] => * Scalable Matrix Extension 2 (SME2) (ARMv9 only). [238] => ** Multi-vector instructions. [239] => ** Multi-vector predicates. [240] => ** 2b/4b weight compression. [241] => ** 1b binary networks. [242] => ** Range Prefetch. [243] => * Guarded Control Stack (GCS) (ARMv9 only). [244] => * Confidential Computing. [245] => ** Memory Encryption Contexts. [246] => ** Device Assignment. [247] => [248] => == {{anchor|ARM8-R}}ARM-R (real-time architecture) == [249] => {{Expand section|1=examples and additional citations|section=1|date=May 2021|small=no|talksection=Talk:AArch64}} [250] => Optional AArch64 support was added to the Armv8-R profile, with the first Arm core implementing it being the Cortex-R82.{{cite web|url=https://www.anandtech.com/show/16056/arm-announces-cortexr82-first-64bit-real-time-processor|title=ARM Announced Cortex-R82: First 64-bit Real Time Processor|first=Andrei|last=Frumusanu|date=3 September 2020|website=[[AnandTech]]}} It adds the A64 instruction set, with some changes to the memory barrier instructions.{{cite web|url=https://developer.arm.com/documentation/ddi0600/ac|title=Arm Architecture Reference Manual Supplement - Armv8, for Armv8-R AArch64 architecture profile|publisher=[[Arm Ltd.]]}} [251] => [252] => == References == [253] => {{Reflist}} [254] => [255] => [[Category:Computer-related introductions in 2011]] [256] => [[Category:ARM architecture]] [257] => [[Category:64-bit computers]] [] => )
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AArch64

AArch64 is a 64-bit instruction set architecture (ISA) developed by ARM Holdings specifically for its ARMv8-A processors. It is the successor to the older ARMv7 architecture, which was primarily used in 32-bit systems.

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It is the successor to the older ARMv7 architecture, which was primarily used in 32-bit systems. AArch64 was designed to provide enhanced performance, power efficiency, and support for larger memory addressing capabilities. The AArch64 ISA supports a wide range of applications, including mobile devices, servers, embedded systems, and high-performance computing. It features a larger number of general-purpose registers, a new exception model, and improved instruction execution capabilities compared to its predecessor. One of the key features of AArch64 is the compatibility with AArch32, which allows the execution of 32-bit applications on 64-bit systems. This backward compatibility is achieved through a new execution state known as AArch32 in AArch64 processors, providing a seamless transition for existing software. AArch64 processors are used in a variety of devices, including smartphones, tablets, and laptops. They offer significant improvements in performance and power efficiency compared to their predecessors, allowing for better multitasking, faster processing speeds, and improved graphics capabilities. As a widely used architecture, AArch64 has gained support from various operating systems, including Android, Linux, and Windows. This support ensures a wide range of software compatibility and availability for devices running on AArch64 processors. In conclusion, AArch64 is a 64-bit instruction set architecture developed by ARM Holdings that offers enhanced performance, power efficiency, and compatibility with previous ARM versions. It is widely used in a range of devices and supported by various operating systems.

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